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TMS626812B PDF预览

TMS626812B

更新时间： 2024-10-28 08:41:19
品牌 Logo 应用领域
德州仪器 - TI 存储
页数 文件大小 规格书
40页 611K
描述
1,048,576 BY 8-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES

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TMS626812B 数据手册

 浏览型号TMS626812B的Datasheet PDF文件第2页浏览型号TMS626812B的Datasheet PDF文件第3页浏览型号TMS626812B的Datasheet PDF文件第4页浏览型号TMS626812B的Datasheet PDF文件第5页浏览型号TMS626812B的Datasheet PDF文件第6页浏览型号TMS626812B的Datasheet PDF文件第7页 
TMS626812B  
1 048 576 BY 8-BIT BY 2-BANK  
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES  
SMOS693A – OCTOBER 1997 – REVISED APRIL 1998  
TMS626812B  
DGE PACKAGE  
( TOP VIEW )  
Organization  
1048576 by 8 Bits by 2 Banks  
3.3-V Power Supply (±10% Tolerance)  
Two Banks for On-Chip Interleaving  
(Gapless Accesses)  
1
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
V
V
SS  
DQ7  
CC  
2
DQ0  
High Bandwidth – Up to 125-MHz Data  
Rates  
3
V
V
SSQ  
DQ6  
SSQ  
DQ1  
4
CAS Latency (CL) Programmable to  
2 or 3 Cycles From Column-Address Entry  
5
V
V
CCQ  
DQ5  
CCQ  
DQ2  
6
Burst Sequence Programmable to Serial or  
Interleave  
7
V
V
SSQ  
DQ4  
SSQ  
DQ3  
8
Burst Length Programmable to 1, 2, 4, or 8  
9
V
V
CCQ  
CCQ  
NC  
Chip Select and Clock Enable for Enhanced  
System Interfacing  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
NC  
NC  
DQM  
CLK  
CKE  
NC  
A9  
NC  
W
Cycle-by-Cycle DQ Bus Mask Capability  
Auto-Refresh and Self-Refresh Capabilities  
4K Refresh (Total for Both Banks)  
CAS  
RAS  
CS  
High-Speed, Low-Noise, Low-Voltage TTL  
(LVTTL) Interface  
A11  
A10  
A0  
A8  
Power-Down Mode  
A7  
Compatible With JEDEC Standards  
Pipeline Architecture  
A1  
A6  
A2  
A5  
Temperature Ranges  
Operating, 0°C to 70°C  
Storage, – 55°C to 150°C  
A3  
A4  
V
V
SS  
CC  
Intel PC100 Compliant (-8A, -8, and  
-10 Devices)  
PIN NOMENCLATURE  
A0–A10 Address Inputs  
Performance Ranges:  
A0–A10 Row Addresses  
SYNCHRONOUS  
CLOCK  
CYCLE TIME  
ACCESS TIME  
(CLOCK TO  
OUTPUT)  
REFRESH  
TIME  
INTERVAL  
A0–A8 Column Addresses (for TMS626812B)  
A10 Automatic-Precharge Select  
Bank Select  
Column-Address Strobe  
Clock Enable  
A11  
CAS  
CKE  
CLK  
CS  
t
t
t
t
AC2  
(CL=2)  
CK3  
†
CK2  
AC3  
(CL=2)  
(CL=3)  
(CL =3)  
’626812B-8  
’626812B-8A  
’626812B-10  
8 ns  
10 ns  
15 ns  
15 ns  
6 ns  
6 ns  
6 ns  
7 ns  
64 ms  
64 ms  
64 ms  
System Clock  
Chip Select  
8 ns  
10 ns  
7.5 ns  
7.5 ns  
DQ[0:7] SDRAM Data Input/Output (TMS626812B)  
DQM  
NC  
RAS  
Data-Input/Data-Output Mask Enable  
No External Connect  
Row-Address Strobe  
Power Supply (3.3-V Typical)  
Power Supply for Output Drivers  
(3.3-V Typical)  
†
CL = CAS latency  
V
V
CC  
CCQ  
V
V
W
Ground  
Ground for Output Drivers  
Write Enable  
SS  
SSQ  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1998, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
1234567...40

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