TMS664164

更新时间： 2024-10-27 22:49:39

品牌	Logo	应用领域
德州仪器 - TI		存储
页数	文件大小	规格书
56页	956K
描述
4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES

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TMS664164 数据手册

TMS664414, TMS664814, TMS664164

4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK

SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES

SMOS695A – APRIL 1998 – REVISED JULY 1998

Organization . . .

Pipeline Architecture (Single-Cycle

1048576 x 16 Bits x 4 Banks

2097152 x 8 Bits x 4 Banks

4194304 x 4 Bits x 4 Banks

Architecture)

Single Write/Read Burst

Self-Refresh Capability (Every 16 s)

3.3-V Power Supply (±10% Tolerance)

Low-Noise, Low-Voltage

Transistor-Transistor Logic (LVTTL)

Interface

Four Banks for On-Chip Interleaving for

x8/x16 (Gapless Access) Depending on

Organizations

Power-Down Mode

High Bandwidth – Up to 125-MHz Data

Rates

Compatible With JEDEC Standards

16K RAS-Only Refresh (Total for All Banks)

4K Auto Refresh (Total for All Banks)/64 ms

Burst Length Programmable to 1, 2, 4, 8

Programmable Output Sequence – Serial or

Interleave

Automatic Precharge and Controlled

Precharge

Chip-Select and Clock-Enable for

Enhanced-System Interfacing

Burst Interruptions Supported:

– Read Interruption

– Write Interruption

Cycle-by-Cycle DQ Bus Mask Capability

Only x16 SDRAM Configuration Supports

Upper-/Lower-Byte Masking Control

– Precharge Interruption

Support Clock-Suspend Operation (Hold

Command)

Programmable CAS Latency From Column

Address

Intel PC100 Compliant (-8 and -8A parts)

Performance Ranges:

SYNCHRONOUS

CLOCK CYLE

TIME

ACCESS TIME

CLOCK TO

OUTPUT

REFRESH

INTERVAL

REF

CK3

CK2

AC3

AC2

’664xx4-8

’664xx4-8A

’664xx4-10

8 ns

10 ns

15 ns

6 ns

64 ms

7.5 ns

10 ns

7.5 ns

description

The TMS664xx4 series are 67108864-bit synchronous dynamic random-access memory (SDRAM) devices

which are organized as follow:

Four banks of 1 048 576 words with 16 bits per word

Four banks of 2097152 words with 8 bits per word

Four banks of 4194304 words with 4 bits per word

All inputs and outputs of the TMS664xx4 series are compatible with the LVTTL interface.

The SDRAM employs state-of-the-art technology for high-performance, reliability, and low power. All inputs and

outputs are synchronized with the CLK input to simplify system design and to enhance use with high-speed

microprocessors and caches.

The TMS664xx4 SDRAM is available in a 400-mil, 54-pin surface-mount thin small-outline package (TSOP)

(DGE suffix).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

12 3 4 5 6 7...56

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与TMS664164相关器件

型号	品牌	获取价格	描述	数据表
TMS66416410	TI	获取价格	4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RA
TMS664164-10DGE	TI	获取价格	4MX16 SYNCHRONOUS DRAM, 7.5ns, PDSO54
TMS664164-10DGER	TI	获取价格	4MX16 CACHE DRAM, 7.5ns, PDSO54, PLASTIC, TSOP2-54
TMS664164-12DGE	TI	获取价格	4MX16 CACHE DRAM, 8ns, PDSO54
TMS664164-12DGER	TI	获取价格	4MX16 CACHE DRAM, 8ns, PDSO54, PLASTIC, TSOP2-54
TMS6641648	TI	获取价格	4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RA
TMS6641648A	TI	获取价格	4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RA
TMS664164-8ADGE	TI	获取价格	4MX16 SYNCHRONOUS DRAM, 6ns, PDSO54, 0.400 INCH, 0.80 MM PITCH, PLASTIC, TSOP2-54
TMS664164-8DGE	TI	获取价格	4MX16 SYNCHRONOUS DRAM, 6ns, PDSO54, 0.400 INCH, 0.80 MM PITCH, PLASTIC, TSOP2-54
TMS664164DGE-10	TI	获取价格	4MX16 SYNCHRONOUS DRAM, 7.5ns, PDSO54, 0.400 INCH, 0.80 MM PITCH, PLASTIC, TSOP2-54

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