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TMS320UC5409GGUR80 PDF预览

TMS320UC5409GGUR80

更新时间： 2024-10-27 15:54:51
品牌 Logo 应用领域
德州仪器 - TI 时钟外围集成电路
页数 文件大小 规格书
80页 1086K
描述
Digital Signal Processor 144-BGA MICROSTAR -40 to 100

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中文翻译

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TMS320UC5409GGUR80 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：LFBGA,针数：144
Reach Compliance Code：unknownHTS代码：8542.31.00.01
Factory Lead Time：1 week风险等级：5.76
其他特性：ALSO REQUIRES 3.3V SUPPLY地址总线宽度：23
桶式移位器：YES边界扫描：YES
最大时钟频率：20 MHz外部数据总线宽度：16
格式：FIXED POINT内部总线架构：MULTIPLE
JESD-30 代码：S-PBGA-B144JESD-609代码：e0
长度：12 mm低功率模式：YES
湿度敏感等级：3端子数量：144
最高工作温度：100 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：LFBGA
封装形状：SQUARE封装形式：GRID ARRAY, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：220认证状态：Not Qualified
座面最大高度：1.4 mm最大供电电压：1.98 V
最小供电电压：1.71 V标称供电电压：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子节距：0.8 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：12 mmuPs/uCs/外围集成电路类型：DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches：1

TMS320UC5409GGUR80 数据手册

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SPRS101E − APRIL 1999 − REVISED OCTOBER 2008  
D
D
D
Advanced Multibus Architecture With Three  
Separate 16-Bit Data Memory Buses and  
One Program Memory Bus  
D
D
D
D
Arithmetic Instructions With Parallel Store  
and Parallel Load  
Conditional Store Instructions  
Fast Return From Interrupt  
40-Bit Arithmetic Logic Unit (ALU),  
Including a 40-Bit Barrel Shifter and Two  
Independent 40-Bit Accumulators  
On-Chip Peripherals  
− Software-Programmable Wait-State  
Generator and Programmable Bank  
Switching  
− On-Chip Phase-Locked Loop (PLL) Clock  
Generator With Internal Oscillator or  
External Clock Source  
− Three Multichannel Buffered Serial Ports  
(McBSPs)  
− Enhanced 8-Bit Parallel Host-Port  
Interface With 16-Bit Data/Addressing  
− One 16-Bit Timer  
17- × 17-Bit Parallel Multiplier Coupled to a  
40-Bit Dedicated Adder for Non-Pipelined  
Single-Cycle Multiply/Accumulate (MAC)  
Operation  
D
D
D
Compare, Select, and Store Unit (CSSU) for  
the Add/Compare Selection of the Viterbi  
Operator  
Exponent Encoder to Compute an  
Exponent Value of a 40-Bit Accumulator  
Value in a Single Cycle  
− Six-Channel Direct Memory Access  
(DMA) Controller  
Two Address Generators With Eight  
Auxiliary Registers and Two Auxiliary  
Register Arithmetic Units (ARAUs)  
D
Power Consumption Control With IDLE1,  
IDLE2, and IDLE3 Instructions With  
Power-Down Modes  
D
D
Data Bus With a Bus-Holder Feature  
Extended Addressing Mode for 8M × 16-Bit  
Maximum Addressable External Program  
Space  
D
D
CLKOUT Off Control to Disable CLKOUT  
On-Chip Scan-Based Emulation Logic,  
†
IEEE Std 1149.1 (JTAG) Boundary Scan  
D
D
D
D
D
D
16K x 16-Bit On-Chip ROM  
Logic  
32K x 16-Bit Dual-Access On-Chip RAM  
D
12.5-ns Single-Cycle Fixed-Point  
Instruction Execution Time (80 MIPS)  
Single-Instruction-Repeat and  
Block-Repeat Operations for Program Code  
D
1.8-V Core Power Supply  
Block-Memory-Move Instructions for Better  
Program and Data Management  
D
1.8-V to 3.6-V I/O Power Supply Enables  
Operation With a SIngle 1.8-V Supply or  
With Dual Power Supplies  
Instructions With a 32-Bit Long Word  
Operand  
D
Available in a 144-Pin Plastic Thin Quad  
Flatpack (TQFP) (PGE Suffix) and a 144-Pin  
Ball Grid Array (BGA) (GGU Suffix)  
Instructions With Two- or Three-Operand  
Reads  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
All trademarks are the property of their respective owners.  
†
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.  
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Copyright 2008, Texas Instruments Incorporated  
ꢞ ꢠꢜ ꢙ ꢤ ꢪꢤ ꢙ ꢦ ꢣ ꢤꢚ ꢛꢞ ꢦ ꢝ ꢜ ꢞ ꢢꢭ ꢮꢜ ꢙ ꢣ ꢣꢚ ꢙꢥ ꢦꢛꢩ ꢜ ꢟ ꢤꢣꢥ ꢚꢢꢣ ꢛꢚꢣ ꢤꢙꢜ ꢬ  
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
1234567...80

中文翻译

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