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TMS320V642AZDK7 PDF预览

TMS320V642AZDK7

更新时间： 2024-10-26 23:03:43
品牌 Logo 应用领域
德州仪器 - TI 数字信号处理器
页数 文件大小 规格书
178页 1669K
描述
Video/Imaging Fixed-Point Digital Signal Processor

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TMS320V642AZDK7 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：BGA
包装说明：FBGA, BGA548,26X26,32针数：548
Reach Compliance Code：unknownECCN代码：3A001.A.3
HTS代码：8542.31.00.01风险等级：5.84
其他特性：ALSO REQUIRES 3.3V SUPPLY地址总线宽度：23
桶式移位器：NO位大小：32
边界扫描：YES最大时钟频率：75.19 MHz
外部数据总线宽度：64格式：FIXED POINT
内部总线架构：MULTIPLEJESD-30 代码：S-PBGA-B548
JESD-609代码：e1长度：23 mm
低功率模式：YES湿度敏感等级：4
端子数量：548最高工作温度：90 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：FBGA封装等效代码：BGA548,26X26,32
封装形状：SQUARE封装形式：GRID ARRAY, FINE PITCH
峰值回流温度（摄氏度）：260电源：1.4,3.3 V
认证状态：Not QualifiedRAM（字数）：4096
座面最大高度：2.8 mm子类别：Digital Signal Processors
最大供电电压：1.44 V最小供电电压：1.36 V
标称供电电压：1.4 V表面贴装：YES
技术：CMOS温度等级：OTHER
端子面层：Tin/Silver/Copper (Sn/Ag/Cu)端子形式：BALL
端子节距：0.8 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：23 mm
uPs/uCs/外围集成电路类型：DIGITAL SIGNAL PROCESSOR, OTHERBase Number Matches：1

TMS320V642AZDK7 数据手册

 浏览型号TMS320V642AZDK7的Datasheet PDF文件第2页浏览型号TMS320V642AZDK7的Datasheet PDF文件第3页浏览型号TMS320V642AZDK7的Datasheet PDF文件第4页浏览型号TMS320V642AZDK7的Datasheet PDF文件第5页浏览型号TMS320V642AZDK7的Datasheet PDF文件第6页浏览型号TMS320V642AZDK7的Datasheet PDF文件第7页 
TMS320DM642  
Video/Imaging Fixed-Point Digital Signal Processor  
www.ti.com  
SPRS200J–JULY 2002–REVISED AUGUST 2005  
1 TMS320DM642 Video/Imaging Fixed-Point Digital Signal Processor  
1.1 Features  
Memory Space  
•
High-Performance Digital Media Processor  
–
–
–
–
–
2-, 1.67-, 1.39-ns Instruction Cycle Time  
500-, 600-, 720-MHz Clock Rate  
Eight 32-Bit Instructions/Cycle  
4000, 4800, 5760 MIPS  
•
•
Enhanced Direct-Memory-Access (EDMA)  
Controller (64 Independent Channels)  
10/100 Mb/s Ethernet MAC (EMAC)  
–
–
–
IEEE 802.3 Compliant  
Media Independent Interface (MII)  
8 Independent Transmit (TX) Channels and  
1 Receive (RX) Channel  
Fully Software-Compatible With C64x™  
•
VelociTI.2™ Extensions to VelociTI™  
Advanced Very-Long-Instruction-Word (VLIW)  
TMS320C64x™ DSP Core  
•
•
Management Data Input/Output (MDIO)  
Three Configurable Video Ports  
–
Eight Highly Independent Functional Units  
With VelociTI.2™ Extensions:  
–
Providing a Glueless I/F to Common Video  
Decoder and Encoder Devices  
•
Six ALUs (32-/40-Bit), Each Supports  
Single 32-Bit, Dual 16-Bit, or Quad 8-Bit  
Arithmetic per Clock Cycle  
–
Supports Multiple Resolutions/Video Stds  
•
VCXO Interpolated Control Port (VIC)  
Supports Audio/Video Synchronization  
•
Two Multipliers Support Four 16 x 16-Bit  
Multiplies (32-Bit Results) per Clock  
Cycle or Eight 8 x 8-Bit Multiplies (16-Bit  
Results) per Clock Cycle  
–
•
•
Host-Port Interface (HPI) [32-/16-Bit]  
32-Bit/66-MHz, 3.3-V Peripheral Component  
Interconnect (PCI) Master/Slave Interface  
Conforms to PCI Specification 2.2  
–
Load-Store Architecture With Non-Aligned  
Support  
64 32-Bit General-Purpose Registers  
Instruction Packing Reduces Code Size  
All Instructions Conditional  
–
–
–
•
Multichannel Audio Serial Port (McASP)  
–
–
Eight Serial Data Pins  
Wide Variety of I2S and Similar Bit Stream  
Format  
•
•
Instruction Set Features  
–
–
–
–
–
Byte-Addressable (8-/16-/32-/64-Bit Data)  
8-Bit Overflow Protection  
Bit-Field Extract, Set, Clear  
Normalization, Saturation, Bit-Counting  
VelociTI.2™ Increased Orthogonality  
–
Integrated Digital Audio I/F Transmitter  
Supports S/PDIF, IEC60958-1, AES-3,  
CP-430 Formats  
•
•
•
•
•
•
Inter-Integrated Circuit (I2C Bus™)  
Two Multichannel Buffered Serial Ports  
Three 32-Bit General-Purpose Timers  
Sixteen General-Purpose I/O (GPIO) Pins  
Flexible PLL Clock Generator  
L1/L2 Memory Architecture  
–
–
–
128K-Bit (16K-Byte) L1P Program Cache  
(Direct Mapped)  
128K-Bit (16K-Byte) L1D Data Cache (2-Way  
Set-Associative)  
2M-Bit (256K-Byte) L2 Unified Mapped  
RAM/Cache (Flexible RAM/Cache  
Allocation)  
IEEE-1149.1 (JTAG) Boundary-  
Scan-Compatible  
•
•
548-Pin Ball Grid Array (BGA) Package  
(GDK and ZDK Suffixes), 0.8-mm Ball Pitch  
•
•
Endianess: Little Endian, Big Endian  
64-Bit External Memory Interface (EMIF)  
548-Pin Ball Grid Array (BGA) Package  
(GNZ and ZNZ Suffixes), 1.0-mm Ball Pitch  
•
•
•
0.13-µm/6-Level Cu Metal Process (CMOS)  
3.3-V I/O, 1.2-V Internal (-500)  
–
Glueless Interface to Asynchronous  
Memories (SRAM and EPROM) and  
Synchronous Memories (SDRAM, SBSRAM,  
ZBT SRAM, and FIFO)  
3.3-V I/O, 1.4-V Internal (A-500, A-600, -600,  
-720)  
•
1024M-Byte Total Addressable External  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this document.  
Windows is a registered trademark of Microsoft Corporation.  
I2C Bus is a trademark of Philips Electronics N.V..  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2002–2005, Texas Instruments Incorporated  
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