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TMS320UC5409PGE PDF预览

TMS320UC5409PGE

更新时间： 2024-10-26 22:08:27
品牌 Logo 应用领域
德州仪器 - TI 数字信号处理器
页数 文件大小 规格书
74页 1027K
描述
FIXED-POINT DIGITAL SIGNAL PROCESSOR

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TMS320UC5409PGE 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：LFQFP, QFP144,.87SQ,20
针数：144Reach Compliance Code：not_compliant
ECCN代码：3A991.A.2HTS代码：8542.31.00.01
风险等级：5.89其他特性：ALSO REQUIRES 3.3V SUPPLY
地址总线宽度：23桶式移位器：YES
位大小：16边界扫描：YES
最大时钟频率：40 MHz外部数据总线宽度：16
格式：FIXED POINT内部总线架构：MULTIPLE
JESD-30 代码：S-PQFP-G144长度：20 mm
低功率模式：YES端子数量：144
最高工作温度：100 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：LFQFP
封装等效代码：QFP144,.87SQ,20封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度（摄氏度）：NOT SPECIFIED
电源：1.8,1.8/3.3 V认证状态：Not Qualified
RAM（字数）：32768座面最大高度：1.6 mm
子类别：Digital Signal Processors最大供电电压：1.89 V
最小供电电压：1.71 V标称供电电压：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：20 mm
uPs/uCs/外围集成电路类型：DIGITAL SIGNAL PROCESSOR, OTHER

TMS320UC5409PGE 数据手册

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TMS320UC5409  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS101A – APRIL 1999 – REVISED AUGUST 1999  
Advanced Multibus Architecture With Three  
Separate 16-Bit Data Memory Buses and  
One Program Memory Bus  
Arithmetic Instructions With Parallel Store  
and Parallel Load  
Conditional Store Instructions  
Fast Return From Interrupt  
40-Bit Arithmetic Logic Unit (ALU),  
Including a 40-Bit Barrel Shifter and Two  
Independent 40-Bit Accumulators  
On-Chip Peripherals  
– Software-Programmable Wait-State  
Generator and Programmable Bank  
Switching  
– On-Chip Phase-Locked Loop (PLL) Clock  
Generator With Internal Oscillator or  
External Clock Source  
17- × 17-Bit Parallel Multiplier Coupled to a  
40-Bit Dedicated Adder for Non-Pipelined  
Single-Cycle Multiply/Accumulate (MAC)  
Operation  
Compare, Select, and Store Unit (CSSU) for  
the Add/Compare Selection of the Viterbi  
Operator  
– Three Multichannel Buffered Serial Ports  
(McBSPs)  
– Enhanced 8-Bit Parallel Host-Port  
Interface With 16-Bit Data/Addressing  
– One 16-Bit Timer  
– Six-Channel Direct Memory Access  
(DMA) Controller  
Exponent Encoder to Compute an  
Exponent Value of a 40-Bit Accumulator  
Value in a Single Cycle  
Two Address Generators With Eight  
Auxiliary Registers and Two Auxiliary  
Register Arithmetic Units (ARAUs)  
Power Consumption Control With IDLE1,  
IDLE2, and IDLE3 Instructions With  
Power-Down Modes  
Data Bus With a Bus-Holder Feature  
Extended Addressing Mode for 8M × 16-Bit  
Maximum Addressable External Program  
Space  
CLKOUT Off Control to Disable CLKOUT  
On-Chip Scan-Based Emulation Logic,  
†
IEEE Std 1149.1 (JTAG) Boundary Scan  
16K x 16-Bit On-Chip ROM  
Logic  
32K x 16-Bit Dual-Access On-Chip RAM  
12.5-ns Single-Cycle Fixed-Point  
Instruction Execution Time (80 MIPS)  
Single-Instruction-Repeat and  
Block-Repeat Operations for Program Code  
1.8-V Core Power Supply  
Block-Memory-Move Instructions for Better  
Program and Data Management  
1.8-V to 3.6-V I/O Power Supply Enables  
Operation With a SIngle 1.8-V Supply or  
With Dual Power Supplies  
Instructions With a 32-Bit Long Word  
Operand  
Available in a 144-Pin Plastic Thin Quad  
Flatpack (TQFP) (PGE Suffix) and a 144-Pin  
Ball Grid Array (BGA) (GGU Suffix)  
Instructions With Two- or Three-Operand  
Reads  
description  
The TMS320UC5409 fixed-point, digital signal processor (DSP) (hereafter referred to as the ’UC5409 unless  
otherwisespecified)isidealforlow-power, high-performanceapplications. Thisprocessoroffersverylowpower  
consumption and the flexibility to support various system voltage configurations. The wide range of I/O voltage  
enables it to operate with a single 1.8-V power supply or with dual power supplies for mixed voltage systems.  
This feature eliminates the need for external level-shifting and reduces power consumption in emerging sub-3V  
systems.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
†
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.  
Copyright 1999, Texas Instruments Incorporated  
ADVANCE INFORMATION concerns new products in the sampling or  
preproduction phase of development. Characteristic data and other  
specifications are subject to change without notice.  
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
1234567...74

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