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TMS320UVC5402PGE30 PDF预览

TMS320UVC5402PGE30

更新时间: 2024-10-27 19:58:55
品牌 Logo 应用领域
德州仪器 - TI 时钟外围集成电路
页数 文件大小 规格书
60页 767K
描述
16-BIT, 30MHz, OTHER DSP, PQFP144, PLASTIC, QFP-144

TMS320UVC5402PGE30 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:LFQFP,针数:144
Reach Compliance Code:unknownECCN代码:3A991.A.2
HTS代码:8542.31.00.01风险等级:5.84
地址总线宽度:20桶式移位器:YES
边界扫描:YES最大时钟频率:30 MHz
外部数据总线宽度:16格式:FIXED POINT
内部总线架构:MULTIPLEJESD-30 代码:S-PQFP-G144
长度:20 mm低功率模式:YES
端子数量:144最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH认证状态:Not Qualified
座面最大高度:1.6 mm最大供电电压:1.32 V
最小供电电压:1.14 V标称供电电压:1.2 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
宽度:20 mmuPs/uCs/外围集成电路类型:DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches:1

TMS320UVC5402PGE30 数据手册

 浏览型号TMS320UVC5402PGE30的Datasheet PDF文件第2页浏览型号TMS320UVC5402PGE30的Datasheet PDF文件第3页浏览型号TMS320UVC5402PGE30的Datasheet PDF文件第4页浏览型号TMS320UVC5402PGE30的Datasheet PDF文件第5页浏览型号TMS320UVC5402PGE30的Datasheet PDF文件第6页浏览型号TMS320UVC5402PGE30的Datasheet PDF文件第7页 
TMS320UVC5402  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS100A – APRIL 1999 – REVISED AUGUST 1999  
D
D
D
Advanced Multibus Architecture With Three  
Separate 16-Bit Data Memory Buses and  
One Program Memory Bus  
D
D
D
D
Arithmetic Instructions With Parallel Store  
and Parallel Load  
Conditional Store Instructions  
Fast Return From Interrupt  
40-Bit Arithmetic Logic Unit (ALU),  
Including a 40-Bit Barrel Shifter and Two  
Independent 40-Bit Accumulators  
On-Chip Peripherals  
– Software-Programmable Wait-State  
Generator and Programmable Bank  
Switching  
– On-Chip Phase-Locked Loop (PLL) Clock  
Generator With Internal Oscillator or  
External Clock Source  
– Two Multichannel Buffered Serial Ports  
(McBSPs)  
– Enhanced 8-Bit Parallel Host-Port  
Interface (HPI-8)  
17- × 17-Bit Parallel Multiplier Coupled to a  
40-Bit Dedicated Adder for Non-Pipelined  
Single-Cycle Multiply/Accumulate (MAC)  
Operation  
D
D
D
Compare, Select, and Store Unit (CSSU) for  
the Add/Compare Selection of the Viterbi  
Operator  
Exponent Encoder to Compute an  
Exponent Value of a 40-Bit Accumulator  
Value in a Single Cycle  
– Two 16-Bit Timers  
– Six-Channel Direct Memory Access  
(DMA) Controller  
Two Address Generators With Eight  
Auxiliary Registers and Two Auxiliary  
Register Arithmetic Units (ARAUs)  
D
Power Consumption Control With IDLE1,  
IDLE2, and IDLE3 Instructions With  
Power-Down Modes  
D
D
Data Bus With a Bus-Holder Feature  
Extended Addressing Mode for 1M × 16-Bit  
Maximum Addressable External Program  
Space  
D
D
CLKOUT Off Control to Disable CLKOUT  
On-Chip Scan-Based Emulation Logic,  
IEEE Std 1149.1 (JTAG) Boundary Scan  
D
D
D
D
D
D
4K x 16-Bit On-Chip ROM  
Logic  
16K x 16-Bit Dual-Access On-Chip RAM  
D
33-ns Single-Cycle Fixed-Point Instruction  
Execution Time (30 MIPS)  
Single-Instruction-Repeat and  
Block-Repeat Operations for Program Code  
D
1.2-V Core Power Supply  
Block-Memory-Move Instructions for  
Efficient Program and Data Management  
D
1.2-V to 2.75-V I/O Power Supply Enables  
Operation With a Single 1.2-V Supply or  
With Dual Supplies  
Instructions With a 32-Bit Long Word  
Operand  
D
Available in a 144-Pin Plastic Thin Quad  
Flatpack (TQFP) (PGE Suffix) and a 144-Pin  
Ball Grid Array (BGA) (GGU Suffix)  
Instructions With Two- or Three-Operand  
Reads  
description  
TheTMS320UVC5402fixed-point, digitalsignalprocessor(DSP)(hereafterreferredtoastheUVC5402unless  
otherwise specified) is the industry’s first 1.2-V DSP. This processor offers ultra low power consumption and  
the flexibility to support various system voltage configurations. The wide range of I/O voltage enables it to  
operate with a single 1.2-V power supply or with dual power supplies for mixed voltage systems. This feature  
eliminates the need for external level-shifting and reduces power consumption in emerging sub-3V systems.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCT PREVIEW information concerns products in the formative or  
design phase of development. Characteristic data and other  
specifications are design goals. Texas Instruments reserves the right to  
change or discontinue these products without notice.  
1
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443  

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