TMS320TCI6482
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SPRS246K –APRIL 2005–REVISED MARCH 2012
TMS320TCI6482
Communications Infrastructure Digital Signal Processor
Check for Samples: TMS320TCI6482
1 Features
12
(FPGA, CPLD, ASICs, etc.)
– 32M-Byte Total Addressable External
Memory Space
• High-Performance Communications
Infrastructure DSP (TCI6482)
– 1.17-, 1-, and 0.83-ns Instruction Cycle Time
– 850-MHz, 1-GHz, and 1.2-GHz Clock Rate
– Eight 32-Bit Instructions/Cycle
– 9600 MIPS/MMACS (16-Bits)
• Four 1x Serial RapidIO® Links (or One 4x),
v1.2 Compliant
– 1.25-, 2.5-, 3.125-Gbps Link Rates
– Message Passing, DirectIO Support, Error
Mgmt Extensions, Congestion Control
– Commercial Temperature [0°C to 90°C]
– Extended Temperature [-40°C to 105°C]
• TMS320C64x+™ DSP Core
– IEEE 1149.6 Compliant I/Os
• DDR2 Memory Controller
– Dedicated SPLOOP Instruction
– Compact Instructions (16-Bit)
– Instruction Set Enhancements
– Exception Handling
– Interfaces to DDR2-533 SDRAM
– 32-Bit/16-Bit, 533-MHz (data rate) Bus
– 512M-Byte Total Addressable External
Memory Space
• TMS320C64x+ Megamodule L1/L2 Memory
Architecture:
• EDMA3 Controller (64 Independent Channels)
• 32-/16-Bit Host-Port Interface (HPI)
• 32-Bit 33-/66-MHz, 3.3-V Peripheral Component
Interconnect (PCI) Master/Slave Interface
– 256K-Bit (32K-Byte) L1P Program Cache
[Direct Mapped]
– 256K-Bit (32K-Byte) L1D Data Cache
[2-Way Set-Associative]
– 16M-Bit (2048K-Byte) L2 Unified Mapped
RAM/Cache [Flexible Allocation]
– 256K-Bit (32K-Byte) L2 ROM
– Time Stamp Counter
Conforms to PCI Local Bus Specification (v2.3)
• One Inter-Integrated Circuit (I2C) Bus
• Two McBSPs
• 10/100/1000 Mb/s Ethernet MAC (EMAC)
– IEEE 802.3 Compliant
– Supports Multiple Media Independent
Interfaces (MII, GMII, RMII, and RGMII)
– 8 Independent Transmit (TX) and
8 Independent Receive (RX) Channels
• 2 RSAs for CDMA Processing
– Dedicated RAKE, PATH_SEARCH and
RACH_SEARCH Instructions
– Transmit Processing Capability
• Two 64-Bit General-Purpose Timers,
Configurable as Four 32-Bit Timers
• UTOPIA
• Enhanced Viterbi Decoder Coprocessor (VCP2)
– Supports Over 694 7.95-Kbps AMR
– Programmable Code Parameters
• Enhanced Turbo Decoder Coprocessor (TCP2)
– UTOPIA Level 2 Slave ATM Controller
– 8-Bit Transmit and Receive Operations up to
50 MHz per Direction
– Supports up to Eight 2-Mbps 3GPP
(6 Iterations)
– Programmable Turbo Code and Decoding
Parameters
– User-Defined Cell Format up to 64 Bytes
• VLYNQ™ Port
– Full Duplex Serial Bus
– Up to 4-Bit Transmit, 4-Bit Receive
– Up to 125-MHz Operation
• Endianess: Little Endian, Big Endian
• 64-Bit External Memory Interface (EMIFA)
– Glueless Interface to Asynchronous
Memories (SRAM, Flash, and EEPROM) and
Synchronous Memories (SBSRAM, ZBT
SRAM)
• 16 General-Purpose I/O (GPIO) Pins
• System PLL and PLL Controller
• Secondary PLL and PLL Controller, Dedicated
to EMAC and DDR2 Memory Controller
– Supports Interface to Standard Sync Devices
and Custom Logic
• Advanced Event Triggering (AET) Compatible
1
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2
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