TMS320TCI6486
www.ti.com
SPRS300N–FEBRUARY 2006–REVISED JULY 2011
TMS320TCI6486 Communications Infrastructure Digital Signal Processor
1 Features
1
Congestion Control
IEEE 1149.6 Compliant I/Os
– UTOPIA
• Six On-Chip TMS320C64x+ Megamodules
• Endianess: Little Endian, Big Endian
• C64x+ Megamodule Main Features:
•
•
•
UTOPIA Level 2 Slave ATM Controller
8/16-Bit Transmit and Receive
– High-Performance, Fixed-Point
TMS320C64x+ DSP
Operations up to 50 MHz per Direction
– 500/625/700 MHz
•
User-Defined Cell Format up to 64 Bytes
– Eight 32-Bit Instructions/Cycle
– 4000 MIPS/MMACS (16-Bits) at 500 MHz
– Dedicated SPLOOP Instruction
– Compact Instructions (16-Bit)
– Instruction Set Enhancements
– Exception Handling
– Two 10/100/1000 Mb/s Ethernet MACs
(EMACs)
•
•
Both EMACs are IEEE 802.3 Compliant
EMAC0 Supports:
–
–
MII, RMII, SS-SMII, GMII, and RGMII
8 Independent Transmit (TX)
Channels
– L1/L2 Memory Architecture:
•
•
•
256K-Bit (32K-Byte) L1P Program
RAM/Cache [Direct Mapped, Flexible
Allocation]
256K-Bit (32K-Byte) L1D RAM/Cache
[2-Way Set-Associative, Flexible
Allocation]
4.75M-Bit (608K-Byte) L2 Unified Mapped
RAM/Cache [4-Way Set-Associative,
Flexible Allocation]
–
8 Independent Receive (RX)
Channels
•
EMAC1 Supports:
–
–
RMII, SS-SMII and RGMII
8 Independent Transmit (TX)
Channels
–
8 Independent Receive (RX)
Channels
•
•
•
L1P Memory Controller
L1D Memory Controller
L2 Memory Controller
•
Both EMACs (EMAC0 and EMAC1) Share
MDIO Interface
– 16-Bit Host-Port Interface (HPI)
– One Inter-Integrated Circuit (I2C) Bus
– Six Shared 64-Bit General-Purpose Timers
• System PLL and PLL Controller
– Time Stamp Counter
– One 64-Bit General-Purpose/Watchdog Timer
• Shared Peripherals and Interfaces
• Secondary PLL and PLL Controller, Dedicated
– EDMA Controller
to EMAC
(64 Independent Channels)
• Third PLL and PLL Controller Dedicated to
DDR2 Memory Controller
• 16 General-Purpose I/O (GPIO) Pins
• IEEE-1149.1 (JTAG™)
Boundary-Scan-Compatible
• 737-Pin Ball Grid Array (BGA) Package
(CTZ, GTZ or ZTZ Suffix), 0.8-mm Ball Pitch
• 0.09-μm/7-Level Cu Metal Process (CMOS)
• 3.3-, 1.8-, 1.5-, 1.2-V I/O Supplies
– Shared Memory Architecture
•
•
•
Shared L2 Memory Controller
768K-Byte of RAM
Boot ROM
– Three Telecom Serial Interface Ports (TSIPs)
•
Each TSIP is 8 Links of 8 Mbps per
Direction
– 32-Bit DDR2 Memory Controller (DDR2-533
SDRAM)
• 1.0-/1.1-, 1.2-V Core Supplies
•
256 M-Byte x 2 Addressable Memory
Space
• Commercial Temperature [0°C to 85°C]
• Extended High Temperature [0°C to 100°C]
• Extended Low Temperature [-40°C to 85°C]
• Extended Temperature [-40°C to 100°C]
– Two 1x Serial RapidIO® Links,
v1.2 Compliant
•
•
1.25-, 2.5-, 3.125-Gbps Link Rates
Message Passing, DirectIO Support,
Error Management Extensions, and
1
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PRODUCTION DATA information is current as of publication date.
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