5秒后页面跳转
捷配首页

Datasheet > 微控制器和处理器 > 数字信号处理器> TMS320TCI6489
TMS320TCI6489 PDF预览

TMS320TCI6489

更新时间： 2024-10-27 11:58:23
品牌 Logo 应用领域
德州仪器 - TI 数字信号处理器通信
页数 文件大小 规格书
197页 1481K
描述
TMS320TCI6489 Communications Infrastructure Digital Signal Processor

阅读下载

中文翻译

获取价格

TMS320TCI6489 数据手册

 浏览型号TMS320TCI6489的Datasheet PDF文件第2页浏览型号TMS320TCI6489的Datasheet PDF文件第3页浏览型号TMS320TCI6489的Datasheet PDF文件第4页浏览型号TMS320TCI6489的Datasheet PDF文件第5页浏览型号TMS320TCI6489的Datasheet PDF文件第6页浏览型号TMS320TCI6489的Datasheet PDF文件第7页 
TMS320TCI6489  
www.ti.com  
SPRS626B–NOVEMBER 2009–REVISED APRIL 2011  
TMS320TCI6489 Communications Infrastructure Digital Signal Processor  
1 Features  
12  
– Up to 64 Macro-BTS Users  
• Key Features  
– Up to 160 km cell size  
– High-Performance Communications  
Infrastructure DSP (TCI6489)  
• Six RSAs for CDMA Processing (2 per core)  
– 1.18-ns Instruction Cycle Time  
– 850-MHz Clock Rate  
– 0°C to 100°C Commercial Temperature  
– Dedicated RAKE, PATH_SEARCH and  
RACH_SEARCH Instructions  
– Transmit Processing Capability  
• Enhanced VCP2  
– 3 TMS320C64x+™ DSP Cores; Six RSAs for  
CDMA Processing (2 per core)  
– One Receive Accelerator (RAC)  
– Enhanced VCP2/TCP2  
– Supports Over 694 7.95-Kbps AMR  
• Enhanced Turbo Decoder Coprocessor (TCP2)  
– Supports up to Eight 2-Mbps 3 GPP  
(6 Iterations)  
• Endianness: Little Endian, Big Endian  
• Frame Synchronization Interface  
– Frame Synchronization Interface  
– 16-/32-Bit DDR2-667 Memory Controller  
– EDMA3 Controller  
– Time Alignment Between Internal  
Subsystems, External Devices/System  
– OBSAI RP1 Compliant for Frame Burst Data  
– Antenna Interface  
– One 1.8-V Inter-Integrated Circuit (I2C) Bus  
– Two 1.8-V McBSPs  
– 1000 Mbps Ethernet MAC (EMAC)  
– Six 64-Bit General-Purpose Timers  
– 16 General-Purpose I/O (GPIO) Pins  
– Internal Semaphore Module  
– System PLL and PLL Controller/DDR PLL  
and PLL Controller, Dedicated to DDR2  
Memory Controller  
– Alternate Interfaces for non-RP1 and  
non-UMTS Systems  
• 16-/32-Bit DDR2-667 Memory Controller  
• EDMA3 Controller (64 Independent Channels)  
• Antenna Interface  
– 4 Configurable Links (Full Duplex)  
– Supports OBSAI RP3 Protocol, v1.0:  
768-Mbps, 1.536-, 3.072-Gbps Link Rates  
– Supports CPRI Protocol V2.0: 614.4-Mbps,  
1.2288-, 2.4576-Gbps Link Rates  
– Clock Input Independent or Shared with CPU  
• High-Performance Communications  
Infrastructure DSP (TCI6489)  
– 1.18-ns Instruction Cycle Time  
– 850-MHz Clock Rate  
(Selectable at Boot-Time)  
• One 1.8-V Inter-Integrated Circuit (I2C) Bus  
• Two 1.8-V McBSPs  
• 1000 Mbps Ethernet MAC (EMAC)  
– IEEE 802.3 Compliant  
– Eight 32-Bit Instructions/Cycle  
– 0°C to 100°C Commercial Temperature  
• 3 TMS320C64x+™ DSP Cores  
– Dedicated SPLOOP Instructions  
– Compact Instructions (16-Bit)  
– Exception Handling  
– Supports SGMII, v1.8 Compliant  
– 8 Independent Transmit (TX) and 8  
• TMS320C64x+ Megamodule L1/L2 Memory  
Independent Receive (RX) Channels  
Architecture  
– 256 K-Bit (32 K-Byte) L1P Program Cache  
[Direct Mapped]  
– 256 K-Bit (32 K-Byte) L1D Data Cache  
[2-Way Set-Associative]  
– 24 M-Bit (3072 K-Byte) Total L2 Unified  
• Six 64-Bit General-Purpose Timers  
– Configurable up to Twelve 32-Bit Timers  
– Configurable in a Watchdog Timer mode  
• 16 General-Purpose I/O (GPIO) Pins  
• Internal Semaphore Module  
Mapped RAM/Cache  
– Software Method to Control Access to  
Shared Resources  
– 32 General Purpose Semaphore Resources  
• System PLL and PLL Controller  
– 512 K-Bit (64 K-Byte) L3 ROM  
• One Receive Accelerator (RAC)  
– Performs Chip-Rate RX Functions  
• DDR PLL and PLL Controller, Dedicated to  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
All trademarks are the property of their respective owners.  
2
PRODUCT PREVIEW information concerns products in the formative  
or design phase of development. Characteristic data and other  
specifications are design goals. Texas Instruments reserves the right  
to change or discontinue these products without notice.  
Copyright © 2009–2011, Texas Instruments Incorporated  
 
1234567...197

中文翻译

下载PDF

与TMS320TCI6489相关器件

型号 品牌 获取价格 描述 数据表
TMS320TCI6489CUN TI

获取价格

 		IC 0-BIT, 61.44 MHz, OTHER DSP, PBGA561, 23 X 23 MM, 0.80 MM PITCH, LEAD FREE, PLASTIC, BG
TMS320TCI6489GUN TI

获取价格

 		暂无描述
TMS320TCI6602 TI

获取价格

 		Multicore Fixed and Floating-Point Digital Signal Processor
TMS320TCI6604 TI

获取价格

 		Multicore Fixed and Floating-Point Digital Signal Processor
TMS320TCI6608 TI

获取价格

 		Multicore Fixed and Floating-Point Digital Signal Processor
TMS320TCI6612 TI

获取价格

 		Communications Infrastructure KeyStone SoC
TMS320TCI6612XCMSA2 TI

获取价格

 		Communications Infrastructure KeyStone SoC
TMS320TCI6614 TI

获取价格

 		Communications Infrastructure KeyStone SoC
TMS320TCI6616 TI

获取价格

 		Communications Infrastructure KeyStone SoC
TMS320TCI6618 TI

获取价格

 		Communications Infrastructure KeyStone SoC

与TMS320TCI6489相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证