TMS320TCI6487
TMS320TCI6488
www.ti.com
SPRS358L–APRIL 2007–REVISED APRIL 2011
TMS320TCI6487/8 Communications Infrastructure Digital Signal Processor
1 Features
12
– Extended Temperature:
• Key Features
•
•
1.2-GHz Device: -40°C to 95°C
1.0-GHz Device: -40°C to 100°C
– High-Performance Communications
Infrastructure DSP (TCI6487/8)
– Instruction Cycle Time: 1.25 ns to 0.83 ns
(1.2-GHz Device); 1.25 ns to 1 ns (1-GHz
Device)
– Clock Rate: 800 MHz to 1.2 GHz (1.2-GHz
Device); 800-MHz to 1-GHz (1-GHz Device)
– Commercial Temperature and Extended
Temperature
– 3 TMS320C64x+™ DSP Cores; Six RSAs for
CDMA Processing (2 per core)
– One Receive Accelerator (RAC) [TCI6488
• 3 TMS320C64x+™ DSP Cores
– Dedicated SPLOOP Instructions
– Compact Instructions (16-Bit)
– Exception Handling
• TMS320C64x+ Megamodule L1/L2 Memory
Architecture
– 256 K-Bit (32 K-Byte) L1P Program Cache
[Direct Mapped]
– 256 K-Bit (32 K-Byte) L1D Data Cache
[2-Way Set-Associative]
– 24 M-Bit (3072 K-Byte) Total L2 Unified
Only]
– Enhanced VCP2/TCP2
Mapped RAM/Cache [Flexible Allocation]
– Frame Synchronization Interface
– 16-/32-Bit DDR2-667 Memory Controller
– EDMA3 Controller
– Antenna Interface
– Two 1x Serial RapidIO® Links, v1.2
•
Configurable at boot-time to 1 MB/
1 MB/1 MB or 1.5 MB/1 MB/0.5 MB
– 512 K-Bit (64 K-Byte) L3 ROM
• One Receive Accelerator (RAC) [TCI6488 Only]
– Performs Chip-Rate RX Functions
– Up to 64 Macro-BTS Users
– Up to 160 km cell size
• Six RSAs for CDMA Processing (2 per core)
Compliant
– One 1.8-V Inter-Integrated Circuit (I2C) Bus
– Two 1.8-V McBSPs
– 1000 Mbps Ethernet MAC (EMAC)
– Six 64-Bit General-Purpose Timers
– 16 General-Purpose I/O (GPIO) Pins
– Internal Semaphore Module
– Dedicated RAKE, PATH_SEARCH and
RACH_SEARCH Instructions
– Transmit Processing Capability
• Enhanced VCP2
– System PLL and PLL Controller/DDR PLL
and PLL Controller, Dedicated to DDR2
Memory Controller
– Supports Over 694 7.95-Kbps AMR
• Enhanced Turbo Decoder Coprocessor (TCP2)
– Supports up to Eight 2-Mbps 3 GPP
• High-Performance Communications
(6 Iterations)
• Endianness: Little Endian, Big Endian
• Frame Synchronization Interface
Infrastructure DSP (TCI6487/8)
– Instruction Cycle Time:
•
•
1.2-GHz Device: 1.25-ns to 0.83-ns(1)
1-GHz Device: 1.25-ns to 1-ns
– Time Alignment Between Internal
Subsystems, External Devices/System
– OBSAI RP1 Compliant for Frame Burst Data
– Clock Rate:
•
•
1.2-GHz Device: 800-MHz to 1.2-GHz
1-GHz Device: 800-MHz to 1-GHz
– Alternate Interfaces for non-RP1 and
non-UMTS Systems
– Eight 32-Bit Instructions/Cycle
– Commercial Temperature:
• 16-/32-Bit DDR2-667 Memory Controller
• EDMA3 Controller (64 Independent Channels)
• Antenna Interface
•
•
1.2-GHz Device: 0°C to 95°C
1-GHz Device: 0°C to 100°C
– 6 Configurable Links (Full Duplex)
– Supports OBSAI RP3 Protocol, v1.0:
768-Mbps, 1.536-, 3.072-Gbps Link Rates
– Supports CPRI Protocol V2.0: 614.4-Mbps,
(1) Note: Advance information is presented in this document for
the TCI6487/8 1.2-GHz device. The TCI6487/8 1.0-GHz DSP
is a fully-qualified device.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
ADVANCE INFORMATION concerns new products in the sampling
or preproduction phase of development. Characteristic data and other
specifications are subject to change without notice.
Copyright © 2007–2011, Texas Instruments Incorporated