TMS320UC5402
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS096A – APRIL 1999 – REVISED DECEMBER 1999
D
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Advanced Multibus Architecture With Three
Separate 16-Bit Data Memory Buses and
One Program Memory Bus
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Arithmetic Instructions With Parallel Store
and Parallel Load
Conditional Store Instructions
Fast Return From Interrupt
40-Bit Arithmetic Logic Unit (ALU),
Including a 40-Bit Barrel Shifter and Two
Independent 40-Bit Accumulators
On-Chip Peripherals
– Software-Programmable Wait-State
Generator and Programmable Bank
Switching
– On-Chip Phase-Locked Loop (PLL) Clock
Generator With Internal Oscillator or
External Clock Source
– Two Multichannel Buffered Serial Ports
(McBSPs)
– Enhanced 8-Bit Parallel Host-Port
Interface (HPI-8)
17- × 17-Bit Parallel Multiplier Coupled to a
40-Bit Dedicated Adder for Non-Pipelined
Single-Cycle Multiply/Accumulate (MAC)
Operation
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Compare, Select, and Store Unit (CSSU) for
the Add/Compare Selection of the Viterbi
Operator
Exponent Encoder to Compute an
Exponent Value of a 40-Bit Accumulator
Value in a Single Cycle
– Two 16-Bit Timers
– Six-Channel Direct Memory Access
(DMA) Controller
Two Address Generators With Eight
Auxiliary Registers and Two Auxiliary
Register Arithmetic Units (ARAUs)
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Power Consumption Control With IDLE1,
IDLE2, and IDLE3 Instructions With
Power-Down Modes
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Data Bus With a Bus-Holder Feature
Extended Addressing Mode for 1M × 16-Bit
Maximum Addressable External Program
Space
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CLKOUT Off Control to Disable CLKOUT
On-Chip Scan-Based Emulation Logic,
†
IEEE Std 1149.1 (JTAG) Boundary Scan
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4K x 16-Bit On-Chip ROM
Logic
16K x 16-Bit Dual-Access On-Chip RAM
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12.5-ns Single-Cycle Fixed-Point
Instruction Execution Time (80 MIPS)
Single-Instruction-Repeat and
Block-Repeat Operations for Program Code
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1.8-V Core Power Supply
Block-Memory-Move Instructions for
Efficient Program and Data Management
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1.8-V to 3.6-V I/O Power Supply Enables
Operation With a Single 1.8-V Supply or
with Dual Supplies
Instructions With a 32-Bit Long Word
Operand
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Available in a 144-Pin Plastic Thin Quad
Flatpack (TQFP) (PGE Suffix) and a 144-Pin
Ball Grid Array (BGA) (GGU Suffix)
Instructions With Two- or Three-Operand
Reads
description
The TMS320UC5402 fixed-point, digital signal processor (DSP) (hereafter referred to as the ’UC5402 unless
otherwisespecified)isidealforlow-power, high-performanceapplications. Thisprocessoroffersverylowpower
consumption and the flexibility to support various system voltage configurations. The wide range of I/O voltage
enables it to operate with a single 1.8-V power supply or with dual power supplies for mixed voltage systems.
This feature eliminates the need for external level-shifting and reduces power consumption in emerging sub-3V
systems.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
Copyright 1999, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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