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TMS320TCI6482ZTZ2 PDF预览

TMS320TCI6482ZTZ2

更新时间： 2024-10-27 20:11:11
品牌 Logo 应用领域
德州仪器 - TI 时钟外围集成电路
页数 文件大小 规格书
260页 1730K
描述
64-BIT, 66.6MHz, OTHER DSP, PBGA697, 24 X 24 MM, 0.80 MM PITCH, LEAD FREE, PLASTIC, BGA-697

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TMS320TCI6482ZTZ2 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：BGA
包装说明：24 X 24 MM, 0.80 MM PITCH, LEAD FREE, PLASTIC, BGA-697针数：697
Reach Compliance Code：compliantECCN代码：3A001.A.3
HTS代码：8542.31.00.01风险等级：5.76
Is Samacsys：N地址总线宽度：20
桶式移位器：NO位大小：32
边界扫描：YES最大时钟频率：66.6 MHz
外部数据总线宽度：64格式：FIXED POINT
内部总线架构：MULTIPLEJESD-30 代码：S-PBGA-B697
长度：24 mm低功率模式：YES
端子数量：697封装主体材料：PLASTIC/EPOXY
封装代码：FBGA封装等效代码：BGA697,29X29,32
封装形状：SQUARE封装形式：GRID ARRAY, FINE PITCH
峰值回流温度（摄氏度）：NOT SPECIFIED电源：1.25,1.5/1.8,1.8,3.3 V
认证状态：Not QualifiedRAM（字数）：8192
座面最大高度：3.242 mm子类别：Digital Signal Processors
最大供电电压：1.2875 V最小供电电压：1.2125 V
标称供电电压：1.25 V表面贴装：YES
技术：CMOS端子形式：BALL
端子节距：0.8 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：24 mm
uPs/uCs/外围集成电路类型：DIGITAL SIGNAL PROCESSOR, OTHERBase Number Matches：1

TMS320TCI6482ZTZ2 数据手册

 浏览型号TMS320TCI6482ZTZ2的Datasheet PDF文件第2页浏览型号TMS320TCI6482ZTZ2的Datasheet PDF文件第3页浏览型号TMS320TCI6482ZTZ2的Datasheet PDF文件第4页浏览型号TMS320TCI6482ZTZ2的Datasheet PDF文件第5页浏览型号TMS320TCI6482ZTZ2的Datasheet PDF文件第6页浏览型号TMS320TCI6482ZTZ2的Datasheet PDF文件第7页 
TMS320TCI6482  
www.ti.com  
SPRS246K –APRIL 2005–REVISED MARCH 2012  
TMS320TCI6482  
Communications Infrastructure Digital Signal Processor  
Check for Samples: TMS320TCI6482  
1 Features  
12  
(FPGA, CPLD, ASICs, etc.)  
– 32M-Byte Total Addressable External  
Memory Space  
• High-Performance Communications  
Infrastructure DSP (TCI6482)  
– 1.17-, 1-, and 0.83-ns Instruction Cycle Time  
– 850-MHz, 1-GHz, and 1.2-GHz Clock Rate  
– Eight 32-Bit Instructions/Cycle  
– 9600 MIPS/MMACS (16-Bits)  
• Four 1x Serial RapidIO® Links (or One 4x),  
v1.2 Compliant  
– 1.25-, 2.5-, 3.125-Gbps Link Rates  
– Message Passing, DirectIO Support, Error  
Mgmt Extensions, Congestion Control  
– Commercial Temperature [0°C to 90°C]  
– Extended Temperature [-40°C to 105°C]  
• TMS320C64x+™ DSP Core  
– IEEE 1149.6 Compliant I/Os  
• DDR2 Memory Controller  
– Dedicated SPLOOP Instruction  
– Compact Instructions (16-Bit)  
– Instruction Set Enhancements  
– Exception Handling  
– Interfaces to DDR2-533 SDRAM  
– 32-Bit/16-Bit, 533-MHz (data rate) Bus  
– 512M-Byte Total Addressable External  
Memory Space  
• TMS320C64x+ Megamodule L1/L2 Memory  
Architecture:  
• EDMA3 Controller (64 Independent Channels)  
• 32-/16-Bit Host-Port Interface (HPI)  
• 32-Bit 33-/66-MHz, 3.3-V Peripheral Component  
Interconnect (PCI) Master/Slave Interface  
– 256K-Bit (32K-Byte) L1P Program Cache  
[Direct Mapped]  
– 256K-Bit (32K-Byte) L1D Data Cache  
[2-Way Set-Associative]  
– 16M-Bit (2048K-Byte) L2 Unified Mapped  
RAM/Cache [Flexible Allocation]  
– 256K-Bit (32K-Byte) L2 ROM  
– Time Stamp Counter  
Conforms to PCI Local Bus Specification (v2.3)  
• One Inter-Integrated Circuit (I2C) Bus  
• Two McBSPs  
• 10/100/1000 Mb/s Ethernet MAC (EMAC)  
– IEEE 802.3 Compliant  
– Supports Multiple Media Independent  
Interfaces (MII, GMII, RMII, and RGMII)  
– 8 Independent Transmit (TX) and  
8 Independent Receive (RX) Channels  
• 2 RSAs for CDMA Processing  
– Dedicated RAKE, PATH_SEARCH and  
RACH_SEARCH Instructions  
– Transmit Processing Capability  
• Two 64-Bit General-Purpose Timers,  
Configurable as Four 32-Bit Timers  
• UTOPIA  
• Enhanced Viterbi Decoder Coprocessor (VCP2)  
– Supports Over 694 7.95-Kbps AMR  
– Programmable Code Parameters  
• Enhanced Turbo Decoder Coprocessor (TCP2)  
– UTOPIA Level 2 Slave ATM Controller  
– 8-Bit Transmit and Receive Operations up to  
50 MHz per Direction  
– Supports up to Eight 2-Mbps 3GPP  
(6 Iterations)  
– Programmable Turbo Code and Decoding  
Parameters  
– User-Defined Cell Format up to 64 Bytes  
• VLYNQ™ Port  
– Full Duplex Serial Bus  
– Up to 4-Bit Transmit, 4-Bit Receive  
– Up to 125-MHz Operation  
• Endianess: Little Endian, Big Endian  
• 64-Bit External Memory Interface (EMIFA)  
– Glueless Interface to Asynchronous  
Memories (SRAM, Flash, and EEPROM) and  
Synchronous Memories (SBSRAM, ZBT  
SRAM)  
• 16 General-Purpose I/O (GPIO) Pins  
• System PLL and PLL Controller  
• Secondary PLL and PLL Controller, Dedicated  
to EMAC and DDR2 Memory Controller  
– Supports Interface to Standard Sync Devices  
and Custom Logic  
• Advanced Event Triggering (AET) Compatible  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
All trademarks are the property of their respective owners.  
2
PRODUCTION DATA information is current as of publication date. Products conform to  
specifications per the terms of the Texas Instruments standard warranty. Production  
processing does not necessarily include testing of all parameters.  
Copyright © 2005–2012, Texas Instruments Incorporated  
 
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