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TM2SN64EPH PDF预览

TM2SN64EPH

更新时间: 2024-11-18 11:58:35
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德州仪器 - TI /
页数 文件大小 规格书
15页 263K
描述
SYNCHRONOUS DYNAMIC RAM MODULES

TM2SN64EPH 数据手册

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ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢈꢉ ꢂ ꢊ ꢋ ꢌꢍ ꢊ ꢎ ꢏ ꢂ ꢐ ꢑ ꢅꢆ ꢒꢐ ꢓ ꢀ  
ꢀ ꢁꢆ ꢃ ꢄꢅ ꢆ ꢇꢈꢉ ꢆ ꢊ ꢎ ꢌꢆ ꢊ ꢔ ꢋ ꢆ ꢐ ꢑ ꢅꢆ ꢒꢐ ꢓ ꢀ  
ꢃꢑ ꢄꢕꢉꢖꢗ ꢄꢗ ꢘꢃ ꢙꢑꢄ ꢚꢁ ꢓꢕ ꢖꢚꢁ ꢁꢗ ꢙ ꢘꢛ ꢇꢃ  
SMMS706A − MARCH 1998 − REVISED APRIL 1998  
D
D
Organization:  
− TM2SN64EPH . . . 2 097 152 x 64 Bits  
− TM4SN64EPH . . . 4 194 304 x 64 Bits  
D
High-Speed, Low-Noise, Low-Voltage TTL  
(LVTTL) Interface  
D
Read Latencies 2 and 3 Supported  
Single 3.3-V Power Supply  
( 10% Tolerance)  
D
Support Burst-Interleave and  
Burst-Interrupt Operations  
D
Designed for 66-MHz 4-Clock Systems  
D
D
D
D
D
D
Burst Length Programmable to 1, 2, 4,  
and 8  
D
JEDEC 168-Pin Dual-In-Line Memory  
Module (DIMM) Without Buffer for Use With  
Socket  
Two Banks for On-Chip Interleaving  
(Gapless Access)  
D
D
TM2SN64EPH — Uses Eight 16M-Bit  
Synchronous Dynamic RAMs (SDRAMs)  
(2M × 8-Bit) in Plastic Thin Small-Outline  
Packages (TSOPs)  
Ambient Temperature Range  
0°C to 70°C  
Gold-Plated Contacts  
Pipeline Architecture  
TM4SN64EPH — Uses Sixteen 16M-Bit  
SDRAMs (2M × 8-Bit) in Plastic TSOPs  
Byte-Read/Write Capability  
Serial Presence Detect (SPD) Using  
EEPROM  
D
D
Performance Ranges:  
SYNCHRONOUS  
CLOCK CYCLE  
TIME  
ACCESS TIME  
CLOCK TO  
OUTPUT  
REFRESH  
INTERVAL  
t
t
t
t
AC2  
CK3  
CK2  
AC3  
(CL = 3)  
(CL = 2) (CL = 3) (CL = 2)  
’xSN64EPH-10  
10 ns  
15 ns 7.5 ns 7.5 ns  
64 ms  
CL = CAS latency  
description  
The TM2SN64EPH is a 16M-byte, 168-pin dual-in-line memory module (DIMM). The DIMM is composed of  
eight TMS626812BDGE, 2097152 x 8-bit SDRAMs, each in a 400-mil, 44-pin plastic thin small-outline package  
(TSOP) mounted on a substrate with decoupling capacitors. See the TMS626812B data sheet (literature  
number SMOS693).  
The TM4SN64EPH is a 32M-byte, 168-pin DIMM. The DIMM is composed of sixteen TMS626812BDGE,  
2097152 x 8-bit SDRAMs, each in a 400-mil, 44-pin plastic TSOP mounted on a substrate with decoupling  
capacitors.  
operation  
The TM2SN64EPH operates as eight TMS626812BDGE devices that are connected as shown in the  
TM2SN64EPH functional block diagram. The TM4SN64EPH operates as sixteen TMS626812BDGE devices  
connected as shown in the TM4SN64EPH functional block diagram.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢀꢧ  
Copyright 1998, Texas Instruments Incorporated  
ꢣ ꢧ ꢤ ꢣꢜ ꢝꢱ ꢟꢞ ꢢ ꢪꢪ ꢨꢢ ꢠ ꢢ ꢡ ꢧ ꢣ ꢧ ꢠ ꢤ ꢬ  
1
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  

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