ꢀ ꢁꢂ ꢃ ꢄꢅ ꢂ ꢆꢇꢈ ꢂ ꢉ ꢊ ꢋꢅ ꢉ ꢌ ꢍ ꢂ ꢎ ꢏ ꢅꢂ ꢐꢎ ꢑ ꢀ
ꢀ ꢁꢒ ꢃ ꢄꢅ ꢂ ꢆꢇꢈ ꢒ ꢉ ꢌ ꢋꢒ ꢉ ꢓ ꢊ ꢒ ꢎ ꢏ ꢅꢂ ꢐꢎ ꢑ ꢀ
ꢃꢏ ꢔꢕꢖꢄꢗ ꢔꢗ ꢈꢃ ꢘꢏꢔ ꢙꢁ ꢑꢕ ꢄꢙꢁ ꢁꢗ ꢘ ꢈꢚ ꢆꢃ
SMMS683A − JUNE 1997 − REVISED AUGUST 1997
D
D
Organization
− TM2SR72EPU . . . 2097152 x 72 Bits
− TM4SR72EPU . . . 4194304 x 72 Bits
D
D
D
D
D
D
D
D
D
D
High-Speed, Low-Noise Low-Voltage TTL
(LVTTL) Interface
Byte-Read/Write Capability
Single 3.3-V Power Supply
( 10% Tolerance)
Read Latencies 2 and 3 Supported
Support Burst-Interleave and
Burst-Interrupt Operations
D
Designed for 66-MHz 4-Clock Systems
D
JEDEC 168-Pin Dual-In-Line Memory
Module (DIMM) Without Buffer for Use With
Socket
Burst Length Programmable to 1, 2, 4,
and 8
Two Banks for On-Chip Interleaving
(Gapless Access)
D
TM2SR72EPU — Uses Nine 16M-Bit
Synchronous Dynamic RAMs (SDRAMs)
(2M × 8-Bit) in Plastic Thin Small-Outline
Packages (TSOPs)
Ambient Temperature Range
0°C to 70°C
Gold-Plated Contacts
Pipeline Architecture
D
D
TM4SR72EPU — Uses 18 16M-Bit SDRAMs
(2M × 8-Bit) in Plastic TSOPs
Performance Ranges:
Serial Presence-Detect (SPD) Using
EEPROM
SYNCHRONOUS
CLOCK CYCLE
TIME
ACCESS TIME
(CLOCK TO
OUTPUT)
REFRESH
INTERVAL
t
t
t
t
CK2
CK3
CK2
CK3
†
(CL = 3)
(CL = 2) (CL = 3) (CL = 2)
‡
’xSR72EPU-12A
12 ns
15 ns
18 ns
9 ns
9 ns
9 ns
64 ms
64 ms
’xSR72EPU-12
12 ns
10 ns
†
‡
CL = CAS latency
-12A speed device is supported only at −5% to+10% V
DD
description
The TM2SR72EPU is a 16M-byte, 168-pin dual-in-line memory module (DIMM). The DIMM is composed of nine
TMS626812DGE, 2097152 x 8-bit SDRAMs, each in a 400-mil, 44-pin plastic thin small-outline package
(TSOP) mounted on a substrate with decoupling capacitors. See the TMS626812 data sheet (literature number
SMOS687).
The TM4SR72EPU is a 32M-byte, 168-pin DIMM. The DIMM is composed of eighteen TMS626812DGE,
2097152 x 8-bit SDRAMs, each in a 400-mil, 44-pin plastic TSOP mounted on a substrate with decoupling
capacitors. See the TMS626812 data sheet (literature number SMOS687).
operation
The TM2SR72EPU operates as nine TMS626812DGE devices that are connected as shown in the
TM2SR72EPU functional block diagram. The TM4SR72EPU operates as eighteen TMS626812DGE devices
connected as shown in the TM4SR72EPU functional block diagram.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
ꢇ
ꢇ
ꢄ
ꢗ
ꢪ
ꢘ
ꢥ
ꢈ
ꢕ
ꢣ
ꢀ
ꢤ
ꢑ
ꢞ
ꢗ
ꢜ
ꢔ
ꢝ
ꢘ
ꢙ
ꢀ
ꢙ
ꢛ
ꢜ
ꢦ
ꢝ
ꢞ
ꢤ
ꢟ
ꢠ
ꢡ
ꢡ
ꢢ
ꢢ
ꢛ
ꢛ
ꢞ
ꢞ
ꢜ
ꢜ
ꢛ
ꢣ
ꢣ
ꢧ
ꢤ
ꢥ
ꢟ
ꢟ
ꢦ
ꢦ
ꢜ
ꢢ
ꢡ
ꢠ
ꢣ
ꢣ
ꢞ
ꢝ
ꢧ
ꢀꢦ
ꢥ
ꢨ
ꢣ
ꢩ
ꢛ
ꢤ
ꢡ
ꢣ
ꢢ
ꢛ
ꢢ
ꢞ
ꢟ
ꢜ
ꢥ
ꢪ
ꢡ
ꢜ
ꢢ
ꢢ
ꢦ
ꢣ
ꢫ
Copyright 1997, Texas Instruments Incorporated
ꢟ
ꢞ
ꢤ
ꢢ
ꢞ
ꢟ
ꢠ
ꢢ
ꢞ
ꢣ
ꢧ
ꢛ
ꢝ
ꢛ
ꢤ
ꢦ
ꢟ
ꢢ
ꢬ
ꢢ
ꢦ
ꢟ
ꢞ
ꢝ
ꢭ
ꢡ
ꢑ
ꢜ
ꢠ
ꢦ
ꢣ
ꢢ
ꢡ
ꢜ
ꢪ
ꢡ
ꢟ
ꢪ
ꢮ
ꢡ
ꢢ ꢦ ꢣ ꢢꢛ ꢜꢰ ꢞꢝ ꢡ ꢩꢩ ꢧꢡ ꢟ ꢡ ꢠ ꢦ ꢢ ꢦ ꢟ ꢣ ꢫ
ꢟ
ꢟ
ꢡ
ꢜ
ꢢ
ꢯ
ꢫ
ꢇ
ꢟ
ꢞ
ꢪ
ꢥ
ꢤ
ꢢ
ꢛ
ꢞ
ꢜ
ꢧ
ꢟ
ꢞ
ꢤ
ꢦ
ꢣ
ꢣ
ꢛ
ꢜ
ꢰ
ꢪ
ꢞ
ꢦ
ꢣ
ꢜ
ꢞ
ꢢ
ꢜ
ꢦ
ꢤ
ꢦ
ꢣ
ꢣ
ꢡ
ꢟ
ꢛ
ꢩ
ꢯ
ꢛ
ꢜ
ꢤ
ꢩ
ꢥ
ꢪ
ꢦ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443