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TC51WHM616AXGN70 PDF预览

TC51WHM616AXGN70

更新时间: 2024-02-03 17:09:00
品牌 Logo 应用领域
东芝 - TOSHIBA /
页数 文件大小 规格书
11页 107K
描述
IC 4M X 16 PSEUDO STATIC RAM, 70 ns, PBGA48, 8 X 11 MM, 0.75 MM PITCH, LEAD FREE, PLASTIC, TFBGA-48, Static RAM

TC51WHM616AXGN70 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:BGA包装说明:TFBGA, BGA48,6X8,30
针数:48Reach Compliance Code:unknown
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.81Base Number Matches:1

TC51WHM616AXGN70 数据手册

 浏览型号TC51WHM616AXGN70的Datasheet PDF文件第1页浏览型号TC51WHM616AXGN70的Datasheet PDF文件第2页浏览型号TC51WHM616AXGN70的Datasheet PDF文件第3页浏览型号TC51WHM616AXGN70的Datasheet PDF文件第5页浏览型号TC51WHM616AXGN70的Datasheet PDF文件第6页浏览型号TC51WHM616AXGN70的Datasheet PDF文件第7页 
TC51WHM616AXGN65,70  
AC CHARACTERISTICS AND OPERATING CONDITIONS  
(Ta = −25°C to 85°C, V = 2.6 to 3.3 V) (See Note 5 to 11)  
DD  
TC51WHM616AXGN  
SYMBOL  
PARAMETER  
UNIT  
65  
70  
MIN  
65  
MAX  
10000  
65  
MIN  
70  
MAX  
10000  
70  
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
µs  
ms  
ns  
µs  
RC  
Address Access Time  
ACC  
CO  
Chip Enable ( CE1 ) Access Time  
Output Enable Access Time  
Data Byte Control Access Time  
Chip Enable Low to Output Active  
Output Enable Low to Output Active  
Data Byte Control Low to Output Active  
Chip Enable High to Output High-Z  
Output Enable High to Output High-Z  
Data Byte Control High to Output High-Z  
Output Data Hold Time  
65  
70  
25  
25  
OE  
25  
25  
BA  
10  
0
10  
0
COE  
OEE  
BE  
0
0
20  
20  
20  
20  
20  
20  
OD  
ODO  
BD  
10  
65  
30  
10  
70  
30  
OH  
Page Mode Time  
10000  
30  
10000  
30  
PM  
Page Mode Cycle Time  
PC  
Page Mode Address Access Time  
Page Mode Output Data Hold Time  
Write Cycle Time  
AA  
10  
65  
50  
65  
60  
60  
0
10  
70  
50  
70  
60  
60  
0
AOH  
WC  
WP  
CW  
BW  
AW  
AS  
10000  
10000  
Write Pulse Width  
Chip Enable to End of Write  
Data Byte Control to End of Write  
Address Valid to End of Write  
Address Set-up Time  
Write Recovery Time  
0
0
WR  
ODW  
OEW  
DS  
WE Low to Output High-Z  
WE High to Output Active  
Data Set-up Time  
20  
20  
0
30  
0
0
30  
0
Data Hold Time  
DH  
CE2 Set-up Time  
0
0
CS  
CE2 Hold Time  
300  
10  
0
300  
10  
0
CH  
CE2 Pulse Width  
DPD  
CHC  
CHP  
CE2 Hold from CE1  
CE2 Hold from Power On  
30  
30  
AC TEST CONDITIONS  
PARAMETER  
CONDITION  
30 pF + 1 TTL Gate  
0.2 V, 0.2 V  
Output load  
Input pulse level  
Timing measurements  
Reference level  
V
DD  
V
× 0.5  
× 0.5  
DD  
V
DD  
t , t  
5 ns  
R
F
2002-04-03 4/11  

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