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TC51WKM516AXBN75 PDF预览

TC51WKM516AXBN75

更新时间: 2024-01-25 07:39:13
品牌 Logo 应用领域
东芝 - TOSHIBA /
页数 文件大小 规格书
11页 116K
描述
2,097,152-WORD BY 16-BIT CMOS PSEUDO STATIC RAM

TC51WKM516AXBN75 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:BGA
包装说明:TFBGA, BGA48,6X8,30针数:48
Reach Compliance Code:unknownECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.92
Base Number Matches:1

TC51WKM516AXBN75 数据手册

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TC51WKM516AXBN75  
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS  
2,097,152-WORD BY 16-BIT CMOS PSEUDO STATIC RAM  
DESCRIPTION  
The TC51WKM516AXBN is a 33,554,432-bit pseudo static random access memory(PSRAM) organized as  
2,097,152 words by 16 bits. Using Toshiba’s CMOS technology and advanced circuit techniques, it provides high  
density, high speed and low power. The device uses dual power supplies(2.6 to 3.3 V for core and 1.7 to 2.2 V for  
output buffer). The device also features SRAM-like W/R timing whereby the device is controlled by CE1 , OE , and  
WE on asynchronous. The device has the page access operation. Page size is 8 words. The device also supports  
deep power-down mode, realizing low-power standby.  
Access Times:  
Access Time  
FEATURES  
Organized as 2,097,152 words by 16 bits  
Dual power supplies(2.6 to 3.3 V for core and  
1.7 to 2.2 V for output buffer)  
75 ns  
75 ns  
25 ns  
30 ns  
CE1 Access Time  
OE Access Time  
Page Access Time  
Package:  
Direct TTL compatibility for all inputs and outputs  
Deep power-down mode: Memory cell data invalid  
Page operation mode:  
Page read operation by 8 words  
Logic compatible with SRAM R/W ( WE ) pin  
Standby current  
P-TFBGA48-0607-0.75AZ (Weight:  
g typ.)  
Standby  
Deep power-down standby  
70 µA  
5 µA  
PIN ASSIGNMENT (TOP VIEW)  
PIN NAMES  
1
2
3
4
5
6
A0 to A20  
A0 to A2  
Address Inputs  
Page Address Inputs  
A
B
C
D
E
F
LB  
OE  
UB  
A0  
A3  
A5  
A1  
A4  
A2  
CE2  
I/O1 to I/O16 Data Inputs/Outputs  
I/O9  
CE1 I/O1  
CE1  
CE2  
Chip Enable Input  
Chip select Input  
I/O10 I/O11  
A6  
I/O2  
I/O4  
I/O5  
I/O6  
I/O3  
V
I/O12 A17  
I/O13 NC  
A7  
V
DD  
SS  
WE  
Write Enable Input  
Output Enable Input  
Data Byte Control Inputs  
Power Supply for Core  
Power Supply for Output Buffer  
Ground  
V
A16  
A15  
A13  
A10  
V
DDQ  
SS  
OE  
I/O15 I/O14 A14  
I/O7  
LB , UB  
G
H
I/O16 A19  
A18 A8  
A12  
A9  
WE I/O8  
A11 A20  
V
DD  
V
DDQ  
(FBGA48)  
GND  
NC  
No Connection  
2002-08-22 1/11  

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