TC51WKM516AXGN65,70
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
2,097,152-WORD BY 16-BIT CMOS PSEUDO STATIC RAM
DESCRIPTION
The TC51WKM516AXGN is a 33,554,432-bit pseudo static random access memory(PSRAM) organized as
2,097,152 words by 16 bits. Using Toshiba’s CMOS technology and advanced circuit techniques, it provides high
density, high speed and low power. The device uses dual power supplies(2.6 to 3.1 V for core and 1.7 to 2.2 V for
output buffer). The device also features SRAM-like W/R timing whereby the device is controlled by CE1 , OE , and
WE on asynchronous. The device has the page access operation. Page size is 8 words. The device also supports
deep power-down mode, realizing low-power standby.
•
Access Times:
FEATURES
•
•
Organized as 2,097,152 words by 16 bits
Dual power supplies(2.6 to 3.1 V for core and
1.7 to 2.2 V for output buffer)
TC51WKM516AXGN
65
70
•
•
•
Direct TTL compatibility for all inputs and outputs
Deep power-down mode: Memory cell data invalid
Page operation mode:
Access Time
CE1 Access Time
OE Access Time
Page Access Time
Package:
65 ns
65 ns
25 ns
30 ns
70 ns
70 ns
25 ns
30 ns
Page read operation by 8 words
•
•
Logic compatible with SRAM R/W ( WE ) pin
Standby current
Standby
70 µA
5 µA
•
Deep power-down standby
P-TFBGA48-6mm × 7mm 0.75mm pitch
PIN ASSIGNMENT (TOP VIEW)
PIN NAMES
1
2
3
4
5
6
A0 to A20
A0 to A2
Address Inputs
Page Address Inputs
A
B
C
D
E
F
LB
OE
UB
A0
A3
A5
A1
A4
A2
CE2
I/O1
I/O3
I/O1 to I/O16 Data Inputs/Outputs
I/O9
CE1
I/O2
I/O4
I/O5
I/O6
CE1
CE2
Chip Enable Input
Chip select Input
I/O10 I/O11
A6
V
I/O12 A17
I/O13 NC
A7
V
DD
SS
WE
Write Enable Input
Output Enable Input
Data Byte Control Inputs
Power Supply for Core
Power Supply for Output Buffer
Ground
V
A16
A15
A13
A10
V
DDQ
SS
OE
I/O15 I/O14 A14
I/O7
LB , UB
G
H
I/O16 A19
A18 A8
A12
A9
WE I/O8
A11 A20
V
DD
V
DDQ
(FBGA48)
GND
NC
No Connection
2002-03-05 1/11