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SY100S391 PDF预览

SY100S391

更新时间: 2024-11-05 22:59:23
品牌 Logo 应用领域
麦瑞 - MICREL /
页数 文件大小 规格书
6页 113K
描述
LOW-POWER HEX TTL-TO-PECL TRANSLATOR

SY100S391 数据手册

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LOW-POWER  
SY100S391  
HEX TTL-TO-PECL  
TRANSLATOR  
FEATURES  
DESCRIPTION  
The SY100S391 is a hex TTL-to-PECL translator for  
converting TTL logic levels to 100K logic levels. The unique  
feature of this translator is the ability to do this translation  
using only one +5V supply. The differential outputs allow  
eachcircuittobeusedasaninverting/non-invertingtranslator,  
or as a differential line driver. A common enable (E), when  
LOW, holds all inverting outputs HIGH and all non-inverting  
inputs LOW.  
Operates from a single +5V supply  
Differential PECL outputs  
Function and pinout compatible with Fairchild F100K  
Available in 24-pin CERPACK and 28-pin PLCC  
packages  
The SY100S391 is ideal for those mixed PECL/TTL  
applications which only have a +5V supply available. When  
used in the differential mode, the S391, due to its high  
common mode rejection, overcomes voltage gradients  
between the TTL and PECL ground systems.  
BLOCK DIAGRAM  
E
PIN CONFIGURATIONS  
Q
Q
0
0
D0  
Q
Q
1
1
D1  
D2  
D3  
D4  
D5  
11 10 9  
8 7 6 5  
D
2
12  
13  
14  
15  
16  
17  
18  
4
3
Q
Q
2
2
GND TTL  
GND PECL  
GNDS  
Q
Q
2
2
2
V
V
V
CCA  
Top View  
PLCC  
J28-1  
1
CC  
GND PECL  
E
28  
27  
26  
CC  
Q
Q
3
3
Q
Q
3
3
D
3
19 20 21 22 23 24 25  
Q
Q
4
4
Q
Q
5
5
24 23 22 21 20 19  
18  
D4  
D5  
Q5  
Q5  
Q4  
Q4  
D
D
1
0
1
2
3
4
5
6
17  
16  
15  
14  
13  
Q
Q
Q
Q
0
0
1
1
Top View  
Flatpack  
F24-1  
PIN NAMES  
Pin  
D0 — D5  
Q0 — Q5  
Q0 — Q5  
E
Function  
Data Inputs (TTL)  
Data Outputs (PECL)  
7
8
9 10 11 12  
Inverting Data Outputs (PECL)  
Enable Input (TTL)  
VCCA  
VCCO for ECL Outputs  
Rev.: G  
Amendment:/0  
Issue Date: July, 1999  
1

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