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SY100S370JZ PDF预览

SY100S370JZ

更新时间: 2024-09-15 05:04:27
品牌 Logo 应用领域
麦瑞 - MICREL 解码器逻辑集成电路驱动
页数 文件大小 规格书
8页 98K
描述
UNIVERSAL DEMULTIPLEXER/DECODER

SY100S370JZ 数据手册

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UNIVERSAL  
DEMULTIPLEXER/  
DECODER  
SY100S370  
FEATURES  
DESCRIPTION  
Max. propagation delay of 1200ps  
IEE min. of –92mA  
The SY100S370 is a universal demultiplexer/decoder  
that can be used as either a dual 1-of-4 decoder or as a  
single 1-of-8 decoder and is designed for use in high-  
performance ECL systems. The Mode control (M) input  
determines the function. In the dual 1-of-4 mode, each 4-  
input group has a pair of active-LOW Enable (E) inputs.  
Industry standard 100K ECL levels  
Extended supply voltage option:  
VEE = –4.2V to –5.5V  
Voltage and temperature compensation for improved The Enable pins are assigned such that in the single 1-of-  
noise immunity  
8 mode they can be tied together in pairs to result in two  
active-LOW Enable inputs. E1a will be tied to E1b and E2a  
to E2b.  
The auxiliary inputs (Hn) are used to determine whether  
the outputs are active-HIGH or active-LOW. The address  
Internal 75Kinput pull-down resistors  
60% faster than National or Signetics  
Approximately 40% lower power than Fairchild  
Function and pinout compatible with Fairchild F100K inputs for the dual 1-of-4 mode are A0a, A1a, A0b. A2a is  
unused. In the 1-of-8 mode, the address inputs are A0a,  
A1a, A2a. The inputs on the device have 75Kpull-down  
resistors.  
Available in 24-pin CERPACK and 28-pin PLCC  
packages  
PIN NAMES  
Pin  
Ana, Anb  
Ena, Enb  
M
Function  
Address Inputs (n = 0,1,2)  
Enable Inputs (n = 1,2)  
Mode Control Input  
Ha  
Z0 – Z3 (Z0a – Z3a) Polarity Select Input  
Z4 – Z7 (Z0b – Z3b) Polarity Select Input  
Common Polarity Select Input  
Single 1-of-8 Data Outputs  
Dual 1-of-4 Data Outputs (n = 1...4)  
VEE Substrate  
Hb  
Hc  
Z0 – Z7  
Zna, Znb  
VEES  
VCCA  
VCCO for ECL Outputs  
Rev.: H  
Amendment:/0  
M9999-032406  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: March 2006  

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