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SY100EL91_06 PDF预览

SY100EL91_06

更新时间: 2024-11-02 07:17:11
品牌 Logo 应用领域
麦瑞 - MICREL /
页数 文件大小 规格书
5页 58K
描述
TRIPLE PECL-TO-ECL TRANSLATOR

SY100EL91_06 数据手册

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1  
TRIPLE  
PECL-TO-ECL TRANSLATOR  
SY100EL91  
DESCRIPTION  
FEATURES  
620ps typical propagation delay  
Fully differential design  
The SY100EL91 is a triple PECL-to-ECL translator. It  
receives standard voltage PECL signals and translates  
them to different ECL output signals.  
Supports standard operation  
Available in 20-pin SOIC package  
A VBB output is provided for interfacing with single  
ended PECL signals at the input. If a single ended input  
is to be used, the VBB output should be connected to the  
D input. The active signal would then drive the D input.  
When used, the VBB output should be bypassed to ground  
via a 0.01µF capacitor. The VBB output is designed to act  
as the switching reference for the EL91 under single  
ended input switching conditions. As a result this pin can  
only source/sink up to 0.5mA of current.  
To accomplish the level translation the EL91 requires  
three power rails. The VCC supply should be connected  
to the positive supply, and the VEE pin should be  
connected to the negative power supply. The GND pins  
as expected are connected to the system ground plane.  
Both VEE and VCC should be bypassed to ground via  
0.01µF capacitors.  
Under open input conditions, the D input will be biased  
at VCC/2 and the D input will be pulled to GND. This  
condition will force the Q output to a LOW, ensuring  
stability.  
PIN NAMES  
Pin  
Function  
Dn  
Qn  
PECL Inputs  
ECL Outputs  
PECL_VBB  
PECL Reference Voltage Output  
Rev.: E  
Amendment:/0  
M9999-031306  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: March 2006  

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