Datasheet > SY100EL92ZC

SY100EL92ZC

更新时间： 2024-11-01 22:25:23

品牌	Logo	应用领域
麦瑞 - MICREL		锁存器接口集成电路光电二极管
页数	文件大小	规格书
4页	74K
描述
TRIPLE LVPECL-TO-PECL OR PECL-TO-LVPECL TRANSLATOR

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中文翻译

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数据手册

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SY100EL92ZC 数据手册

TRIPLE LVPECL-TO-PECL

OR PECL-TO-LVPECL

TRANSLATOR

SY100EL92

FEATURES

DESCRIPTION

■ 5V and 3.3V power supplies required

■ Also, supports LVPECL-to-PECL translation

■ 500ps propagation delays

The SY100EL92 is a triple LVPECL-to-PECL or PECL-

to-LVPECL translator. The device receives standard PECL

signals and translates them to differential LVPECL output

signals (or vice versa). SY100EL92 can also be used as a

differential line receiver for PECL-to-PECL or LVPECL-to-

LVPECL signals. However, please note that for the latter

we will need two different power supplies. Please refer to

Function Table for more details.

VBB outputs are provided for interfacing single ended

input signals. If a single ended input is to be used, the VBB

output should be connected to the D input and the active

signal will drive the D input. When used, the VBB should be

bypassed to VCC via a 0.01µF capacitor. The VBB is

designed to act as a switching reference for the SY100EL92

under single ended input conditions. As a result, the pin

can only source/sink 0.5mA of current.

To accomplish the PECL-to-LVPECL level translation,

the SY100EL92 requires three power rails. The VCC and

VCC_VBB supply is to be connected to the standard PECL

supply, the 3.3V supply is to be connected to the VCCO

supply, and GND is connected to the system ground plane.

Both the VCC and VCCO should be bypassed to ground with

a 0.01µF capacitor.

To accomplish the LVPECL-to-PECL level translation,

the SY100EL92 requires three power rails as well. The 5.0V

supply is connected to the VCC and VCCO pins, 3.3V supply

is connected to the VCC_VBB pin and GND is connected to

the system ground plane. VCC_VBB is used to provide a

proper VBB output level if a single ended input is used. For

differential LVPECL input VCC_VBB can be either 3.3V or

5V.

■ Fully differential design

■ Differential line receiver capability

■ Application note

■ Available in 20-pin SOIC package

PIN CONFIGURATION/BLOCK DIAGRAM

VCC_

CCO

VCCO

GND 10

VCC

Under open input conditions, the D input will be biased

at a VCC/2 voltage level and the D input will be pulled to

GND. This condition will force the "Q" output low, ensuring

stability.

SOIC

TOP VIEW

FUNCTION TABLE

PIN NAMES

Function

Vcc

5.0V

Vcco

3.3V

5.0V

3.3V

Vcc_VBB

Function

PECL / LVPECL Inputs

PECL-to-LVPECL

LVPECL-to-PECL

PECL-to-PECL

5.0V

3.3V

5.0V

3.3V

PECL / LVPECL Outputs

PECL / LVPECL Reference Voltage Output

VCC for Output

VBB

LVPECL-to-LVPECL

VCCO

VCC_VBB

GND

VCC

VCC for VBB Output

Common Ground Rail

VCC for Internal Circuitry

Rev.: D

Amendment:/0

Issue Date: January, 1999

12 3 4

中文翻译

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与SY100EL92ZC相关器件

型号	品牌	获取价格	描述	数据表
SY100EL92ZCTR	MICREL	获取价格	TRIPLE LVPECL-TO-PECL OR PECL-TO-LVPECL TRANSLATOR
SY100EL92ZG	MICREL	获取价格	TRIPLE LVPECL-TO-PECL OR PECL-TO-LVPECL TRANSLATOR
SY100EL92ZG	MICROCHIP	获取价格	TRIPLE PECL TO LVPECL TRANSCEIVER, COMPLEMENTARY OUTPUT, PDSO20
SY100EL92ZGTR	MICREL	获取价格	TRIPLE LVPECL-TO-PECL OR PECL-TO-LVPECL TRANSLATOR
SY100EL92ZG-TR	MICROCHIP	获取价格	TRIPLE PECL TO LVPECL TRANSCEIVER, COMPLEMENTARY OUTPUT, PDSO20
SY100EL92ZI	MICREL	获取价格	TRIPLE LVPECL-TO-PECL OR PECL-TO-LVPECL TRANSLATOR
SY100EL92ZI	MICROCHIP	获取价格	PECL to LVPECL Transceiver
SY100EL92ZITR	MICREL	获取价格	TRIPLE LVPECL-TO-PECL OR PECL-TO-LVPECL TRANSLATOR
SY100ELT20V	MICREL	获取价格	5V/3.3V TTL-TO-DIFFERENTIAL PECL TRANSLATOR
SY100ELT20VZC	MICREL	获取价格	5V/3.3V TTL-to-DIFFERENTIAL PECL TRANSLATOR

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