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SY100EL92ZG

更新时间： 2024-01-05 03:44:53
品牌 Logo 应用领域
美国微芯 - MICROCHIP 光电二极管输出元件接口集成电路锁存器
页数 文件大小 规格书
5页 92K
描述
TRIPLE PECL TO LVPECL TRANSCEIVER, COMPLEMENTARY OUTPUT, PDSO20

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SY100EL92ZG 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：SOP, SOP20,.4Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
Factory Lead Time：13 weeks风险等级：5.39
Is Samacsys：N最大延迟：0.63 ns
接口集成电路类型：PECL TO LVPECL TRANSCEIVERJESD-30 代码：R-PDSO-G20
JESD-609代码：e4长度：12.83 mm
湿度敏感等级：2位数：1
功能数量：3端子数量：20
最高工作温度：85 °C最低工作温度：-40 °C
输出锁存器或寄存器：NONE输出极性：COMPLEMENTARY
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP20,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
认证状态：Not Qualified座面最大高度：2.65 mm
最大压摆率：12 mA最大供电电压：5.5 V
最小供电电压：4.5 V标称供电电压：5 V
表面贴装：YES温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：40宽度：7.62 mm
Base Number Matches：1

SY100EL92ZG 数据手册

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NOT RECOMMENDED FOR NEW DESIGNS  
2  
SY100EL92  
TRIPLE LVPECL-TO-PECL  
OR PECL-TO-LVPECL TRANSLATOR  
DESCRIPTION  
FEATURES  
■ 5V and 3.3V power supplies required  
■ Also, supports LVPECL-to-PECL translation  
■ 500ps propagation delays  
The SY100EL92 is a triple LVPECL-to-PECL or PECL-  
to-LVPECL translator. The device receives standard PECL  
signals and translates them to differential LVPECL output  
signals (or vice versa). SY100EL92 can also be used as a  
differential line receiver for PECL-to-PECL or LVPECL-to-  
LVPECL signals. However, please note that for the latter  
we will need two different power supplies. Please refer to  
Function Table for more details.  
VBB outputs are provided for interfacing single ended  
input signals. If a single ended input is to be used, the VBB  
output should be connected to the D input and the active  
signal will drive the D input. When used, the VBB should be  
bypassed to VCC via a 0.01µF capacitor. The VBB is  
designed to act as a switching reference for the SY100EL92  
under single ended input conditions. As a result, the pin  
can only source/sink 0.5mA of current.  
■ Fully differential design  
■ Differential line receiver capability  
■ Application note  
■ Available in 20-pin SOIC package  
To accomplish the PECL-to-LVPECL level translation,  
the SY100EL92 requires three power rails. The VCC and  
VCC_VBB supply is to be connected to the standard PECL  
supply, the 3.3V supply is to be connected to the VCCO  
supply, and GND is connected to the system ground plane.  
Both the VCC and VCCO should be bypassed to ground with  
a 0.01µF capacitor.  
To accomplish the LVPECL-to-PECL level translation,  
the SY100EL92 requires three power rails as well. The 5.0V  
supply is connected to the VCC and VCCO pins, 3.3V supply  
is connected to the VCC_VBB pin and GND is connected to  
the system ground plane. VCC_VBB is used to provide a  
proper VBB output level if a single ended input is used. For  
differential LVPECL input VCC_VBB can be either 3.3V or  
5V.  
Under open input conditions, the D input will be biased  
at a VCC/2 voltage level and the D input will be pulled to  
GND. This condition will force the "Q" output low, ensuring  
stability.  
FUNCTION TABLE  
PIN NAMES  
Function  
Vcc  
5.0V  
5.0V  
5.0V  
5.0V  
Vcco  
3.3V  
5.0V  
5.0V  
3.3V  
Vcc_VBB  
5.0V  
Pin  
Function  
PECL / LVPECL Inputs  
PECL-to-LVPECL  
LVPECL-to-PECL  
PECL-to-PECL  
Dn  
Qn  
3.3V  
PECL / LVPECL Outputs  
PECL / LVPECL Reference Voltage Output  
VCC for Output  
5.0V  
VBB  
LVPECL-to-LVPECL  
3.3V  
VCCO  
VCC_VBB  
GND  
VCC  
VCC for VBB Output  
Common Ground Rail  
VCC for Internal Circuitry  
Rev.: G  
Amendment: /0  
M9999-031306  
hbwhelp@micrel.com or (408) 955-1690  
1
1
Issue Date: March 2006  
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