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SY100ELT21ZCTR

更新时间： 2024-11-30 22:35:03

品牌	Logo	应用领域
麦瑞 - MICREL		锁存器接口集成电路光电二极管
页数	文件大小	规格书
4页	54K
描述
DIFFERENTIAL PECL-to-TTL TRANSLATOR

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中文翻译

获取价格

数据手册

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SY100ELT21ZCTR 数据手册

DIFFERENTIAL

PECL-to-TTL

TRANSLATOR

ClockWorks™

SY10ELT21

SY100ELT21

FEATURES

DESCRIPTION

The SY10/100ELT21 are single differential PECL-to-

TTL translators. Because PECL (Positive ECL) levels are

used, only +5V and ground are required. The small outline

8-lead SOIC package and low skew single gate design

make the ELT21 ideal for applications that require the

translation of a clock or data signal where minimal space,

low power, and low cost are critical.

■ 2.5ns typical propagation delay

■ Low power

■ Differential PECL inputs

■ 24mA TTL outputs

■ Flow-through pinouts

■ Available in 8-pin SOIC package

The V output allow differential single-ended, or AC-

coupled interface to the device. If used, the V

output

should be bypassed to V

with a 0.01µF capacitor.

The ELT21 is available in both ECL standards: the

10ELT is compatible with positive ECL 10H logic levels,

while the 100ELT is compatible with positive ECL 100K

logic levels.

PIN CONFIGURATION/BLOCK DIAGRAM

PIN NAMES

Function

TTL Output

V_CC

D, /D

V_CC

V_BB

GND

Differential PECL Inputs

+5.0V Supply

TTL

PECL

Reference Output

Ground

GND

V_BB

SOIC

TOP VIEW

Rev.: B

Amendment:/0

Issue Date: April 2000

12 3 4

中文翻译

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