SY100ELT22ZCL

更新时间： 2024-01-23 07:31:10

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麦瑞 - MICREL		/
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数据手册

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SY100ELT22ZCL 数据手册

SY10ELT22

SY1^S0^YE¹L⁰⁰T^E2^L2^T22

SY100ELT22

Micrel, Inc.

DUAL TTL-to-DIFFERENTIAL

PECL TRANSLATOR

FEATURES

DESCRIPTION

■ 300ps typical propagation delay

■ <100ps output-to-output skew

■ Differential PECL outputs

The SY10/100ELT22 are dual TTL-to-differential PECL

translators. Because PECL (Positive ECL) levels are

used, only +5V and ground are required. The small outline

8-lead SOIC package and the low skew, dual gate design

of the ELT22 makes it ideal for applications which require

the tranlation of a clock and a data signal.

■ PNP TTL inputs for minimal loading

■ Flow-through pinouts

The ELT22 is available in both ECL standards: the

10ELT is compatible with positive ECL 10H logic levels,

while the 100ELT is compatible with positive ECL 100K

logic levels.

■ Available in 8-pin SOIC package

PIN NAMES

Function

Differential PECL Outputs

TTL Inputs

VCC

GND

+5.0V Supply

Ground

Rev.: G

Amendment: /0

M9999-120705

hbwhelp@micrel.com or (408) 955-1690

Issue Date: December2005

12 3 4 5

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