SY100ELT23ZC

更新时间： 2024-02-08 16:07:01

品牌	Logo	应用领域
麦瑞 - MICREL		锁存器接口集成电路光电二极管
页数	文件大小	规格书
4页	55K
描述
DUAL DIFFERENTIAL PECL-to-TTL TRANSLATOR

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中文翻译

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数据手册

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SY100ELT23ZC 数据手册

DUAL DIFFERENTIAL

PECL-to-TTL

TRANSLATOR

ClockWorks™

SY10ELT23

SY100ELT23

DESCRIPTION

FEATURES

■ 3.0ns typical propagation delay

■ <500ps typical output-to-output skew

■ Differential PECL inputs

The SY10/100ELT23 are dual differential PECL-to-TTL

translators. Because PECL (Positive ECL) levels are

used, only +5V and ground are required. The small outline

8-lead SOIC package and the low skew dual gate design

of the ELT23 makes it ideal for applications which require

the translation of a clock and a data signal.

■ 24mA TTL outputs

■ Flow-through pinouts

The ELT23 is available in both ECL standards: the

10ELT is compatible with positive ECL 10H logic levels,

while the 100ELT is compatible with positive ECL 100K

logic levels.

■ Available in 8-pin SOIC package

PIN NAMES

PIN CONFIGURATION/BLOCK DIAGRAM

Function

TTL Outputs

VCC

Differential PECL Inputs

+5.0V Supply

VCC

GND

PECL

TTL

Ground

GND

SOIC

TOP VIEW

Rev.: G

Amendment: 0

Issue Date: December1999

12 3 4

中文翻译

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与SY100ELT23ZC相关器件

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SY100ELT23ZCL	MICREL	获取价格	ECL to TTL Translator, 2 Func, True Output, BIPolar, PDSO8, PLASTIC, SOIC-8
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SY100ELT23ZITR	MICREL	获取价格	DUAL DIFFERENTIAL PECL-to-TTL TRANSLATOR
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