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SY100ELT21L PDF预览

SY100ELT21L

更新时间: 2024-12-02 14:55:15
品牌 Logo 应用领域
美国微芯 - MICROCHIP /
页数 文件大小 规格书
12页 315K
描述
The SY100ELT21L is a single differential LVPECL to- LVTTL translator s using a single +3.3V p

SY100ELT21L 数据手册

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SY100ELT21L  
3.3V Differential LVPECL-to-LVTTL Translator  
Features  
General Description  
• 3.3V Power Supply  
The SY100ELT21L is  
a
single differential  
LVPECL-to-LVTTL translator that uses a single +3.3V  
power supply. Because LVPECL (low voltage positive  
ECL) levels are used, only +3.3V and ground are  
required. The small outline 8-lead SOIC package and  
low skew single gate design make the ELT21L ideal for  
applications that require the translation of a clock or  
data signal where minimal space, low power, and low  
cost are critical.  
• 2.0 ns Typical Propagation Delay  
• Low Power  
• Differential LVPECL Inputs  
• 24 mA TTL Outputs  
• Flow-Through Pinouts  
• Available in 8-Lead SOIC Package  
VBB allows a differential, single-ended, or AC-coupled  
interface to the device. If used, the VBB output should  
be bypassed to VCC with a 0.01 μF capacitor.  
Under open input conditions, the /D will be biased at a  
VCC/2 voltage level and the D input will be pulled to  
ground. This condition will force the Q output low to  
provide added stability.  
The ELT21L is compatible with positive ECL 100K logic  
levels.  
Package Type  
SY100ELT21L  
8-Lead SOIC  
(Top View)  
NC  
D
1
2
3
8
7
6
5
VCC  
Q
TTL  
PECL  
D
NC  
VBB 4  
GND  
2019 Microchip Technology Inc.  
DS20006213A-page 1  

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