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SY100ELT21LZC PDF预览

SY100ELT21LZC

更新时间: 2024-01-23 18:47:38
品牌 Logo 应用领域
麦瑞 - MICREL /
页数 文件大小 规格书
4页 54K
描述
3.3V DIFFERENTIAL LVPECL-to-LVTTL TRANSLATOR

SY100ELT21LZC 技术参数

生命周期:Not Recommended包装说明:SOP, SOP8,.25
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.59
Is Samacsys:N最大延迟:3 ns
输入特性:DIFFERENTIAL接口集成电路类型:PECL TO TTL TRANSLATOR
JESD-30 代码:R-PDSO-G8长度:4.93 mm
位数:1功能数量:1
端子数量:8最高工作温度:85 °C
最低工作温度:-40 °C输出锁存器或寄存器:NONE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP8,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
座面最大高度:1.73 mm最大压摆率:20 mA
最大供电电压:5.25 V最小供电电压:4.75 V
标称供电电压:5 V表面贴装:YES
技术:ECL温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:3.94 mm
Base Number Matches:1

SY100ELT21LZC 数据手册

 浏览型号SY100ELT21LZC的Datasheet PDF文件第2页浏览型号SY100ELT21LZC的Datasheet PDF文件第3页浏览型号SY100ELT21LZC的Datasheet PDF文件第4页 
3.3V DIFFERENTIAL  
LVPECL-to-LVTTL  
TRANSLATOR  
ClockWorks™  
SY10ELT21L  
SY100ELT21L  
DESCRIPTION  
FEATURES  
3.3V power supply  
The SY10/100ELT21L are single differential LVPECL-  
to-LVTTL translators using a single +3.3V power supply.  
Because LVPECL (Low Voltage Positive ECL) levels are  
used, only +3.3V and ground are required. The small  
outline 8-lead SOIC package and low skew single gate  
design make the ELT21L ideal for applications that require  
the translation of a clock or data signal where minimal  
space, low power, and low cost are critical.  
2.0ns typical propagation delay  
Low power  
Differential LVPECL inputs  
24mA TTL outputs  
Flow-through pinouts  
Available in 8-pin SOIC package  
V
allows a differential, single-ended, or AC-coupled  
BB  
interface to the device. If used, the V output should be  
BB  
bypassed to V  
with 0.01µF capacitor.  
CC  
Under open input conditions, the /D will be biased at a  
/2 voltage level and the D input will be pulled to  
V
CC  
ground. This condition will force the Q output low to  
provide added stability.  
The ELT21L is available in both ECL standards: the  
10ELT is compatible with positive ECL 10H logic levels,  
while the 100ELT is compatible with positive ECL 100K  
logic levels.  
PIN NAMES  
PIN CONFIGURATION/BLOCK DIAGRAM  
Pin  
Function  
Q
TTL Output  
NC  
D
1
2
3
4
8
7
6
5
VCC  
Q
TTL  
D, /D  
VCC  
Differential LVPECL Inputs  
+3.3V Supply  
PECL  
D
NC  
GND  
VBB  
Reference Output  
Ground  
VBB  
GND  
Rev.: B  
Amendment:/0  
Issue Date: April 2000  
1

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