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SY100EL91ZITR PDF预览

SY100EL91ZITR

更新时间: 2024-12-01 03:13:11
品牌 Logo 应用领域
麦瑞 - MICREL 转换器电平转换器驱动程序和接口锁存器接口集成电路光电二极管
页数 文件大小 规格书
5页 57K
描述
3.3V TRIPLE LVPECL-to-ECL OR LVPECL-to-LVECL TRANSLATOR

SY100EL91ZITR 技术参数

是否Rohs认证: 不符合生命周期:Transferred
零件包装代码:SOIC包装说明:SOP, SOP20,.4
针数:20Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.39Is Samacsys:N
最大延迟:0.75 ns接口集成电路类型:PECL TO ECL TRANSLATOR
JESD-30 代码:R-PDSO-G20JESD-609代码:e0
长度:12.83 mm湿度敏感等级:1
标称负供电电压:-4.5 V位数:1
功能数量:3端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出锁存器或寄存器:NONE输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP20,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):240
电源:-4.5 V认证状态:Not Qualified
座面最大高度:2.65 mm子类别:Level Translators
最大供电电压:5.25 V最小供电电压:4.75 V
标称供电电压:5 V表面贴装:YES
技术:ECL100K温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:7.5 mm
Base Number Matches:1

SY100EL91ZITR 数据手册

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1  
TRIPLE  
PECL-TO-ECL TRANSLATOR  
SY100EL91  
DESCRIPTION  
FEATURES  
620ps typical propagation delay  
Fully differential design  
The SY100EL91 is a triple PECL-to-ECL translator. It  
receives standard voltage PECL signals and translates  
them to different ECL output signals.  
Supports standard operation  
Available in 20-pin SOIC package  
A VBB output is provided for interfacing with single  
ended PECL signals at the input. If a single ended input  
is to be used, the VBB output should be connected to the  
D input. The active signal would then drive the D input.  
When used, the VBB output should be bypassed to ground  
via a 0.01µF capacitor. The VBB output is designed to act  
as the switching reference for the EL91 under single  
ended input switching conditions. As a result this pin can  
only source/sink up to 0.5mA of current.  
To accomplish the level translation the EL91 requires  
three power rails. The VCC supply should be connected  
to the positive supply, and the VEE pin should be  
connected to the negative power supply. The GND pins  
as expected are connected to the system ground plane.  
Both VEE and VCC should be bypassed to ground via  
0.01µF capacitors.  
Under open input conditions, the D input will be biased  
at VCC/2 and the D input will be pulled to GND. This  
condition will force the Q output to a LOW, ensuring  
stability.  
PIN NAMES  
Pin  
Function  
Dn  
Qn  
PECL Inputs  
ECL Outputs  
PECL_VBB  
PECL Reference Voltage Output  
Rev.: E  
Amendment:/0  
M9999-031306  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: March 2006  

SY100EL91ZITR 替代型号

型号 品牌 替代类型 描述 数据表
MC100LVEL91DWR2G ONSEMI

类似代替

3.3 V Triple LVPECL Input to −3.3 V to −5.0 V ECL Output Translator
MC100EL91DWG ONSEMI

类似代替

5 V Triple PECL Input to −5 V ECL Output Translator

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