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SY100EL91L PDF预览

SY100EL91L

更新时间: 2024-12-01 14:49:55
品牌 Logo 应用领域
美国微芯 - MICROCHIP /
页数 文件大小 规格书
6页 118K
描述
The SY100EL91L is a triple LVPECL-to-ECL or LVPECL-to-LVECL translator. A VBB?output is provided f

SY100EL91L 数据手册

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SY100EL91L
3.3V TRIPLE LVPECL-to-ECL  
OR LVPECL-to-LVECL TRANSLATOR  
DESCRIPTION  
FEATURES  
The SY100EL91L is a triple LVPECL-to-ECL or  
LVPECL-to-LVECL translator.  
3.3V power supply  
620ps propagation delay  
Fully differential design  
A VBB output is provided for interfacing with single  
ended PECL signals at the input. If a single ended input  
is to be used, the VBB output should be connected to the  
D input. The active signal would then drive the D input.  
When used, the VBB output should be bypassed to ground  
via a 0.01µF capacitor. The VBB output is designed to act  
as the switching reference for the EL91L under single  
ended input switching conditions. As a result this pin can  
only source/sink up to 0.5mA of current.  
Supports low voltage operation  
Available in 20-pin SOIC package  
To accomplish the level translation the EL91L requires  
three power rails. The VCC supply should be connected  
to the positive supply, and the VEE pin should be  
connected to the negative power supply. The GND pins  
as expected are connected to the system ground plane.  
Both VEE and VCC should be bypassed to ground via  
0.01µF capacitors.  
Under open input conditions, the D input will be biased  
at VCC/2 and the D input will be pulled to GND. This  
condition will force the Q output to a LOW, ensuring  
stability.  
PIN NAMES  
FUNCTION TABLE  
Function  
Vcc  
3.3V  
3.3V  
VEE  
Pin  
Function  
LVPECL-to-ECL  
LVPECL-to-LVECL  
–5.0V  
–3.3V  
Dn  
Qn  
PECL Inputs  
ECL Outputs  
PECL_VBB  
PECL Reference Voltage Output  
Rev.: H  
Amendment:/0  
M9999-031306  
hbwhelp@micrel.com or (408) 955-1690  
1
1
Issue Date: December2005  

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