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SY100E111AJI

更新时间： 2024-09-16 22:20:59
品牌 Logo 应用领域
麦瑞 - MICREL 时钟驱动器
页数 文件大小 规格书
5页 87K
描述
5V/3.3V 1:9 DIFFERENTIAL CLOCK DRIVER w/o ENABLE

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中文翻译

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SY100E111AJI 技术参数

是否Rohs认证： 不符合生命周期：Transferred
包装说明：QCCJ, LDCC28,.5SQReach Compliance Code：not_compliant
HTS代码：8542.39.00.01风险等级：5.06
系列：100E输入调节：DIFFERENTIAL
JESD-30 代码：S-PQCC-J28JESD-609代码：e0
长度：11.48 mm逻辑集成电路类型：LOW SKEW CLOCK DRIVER
湿度敏感等级：1功能数量：1
反相输出次数：端子数量：28
实输出次数：9最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装等效代码：LDCC28,.5SQ
封装形状：SQUARE封装形式：CHIP CARRIER
峰值回流温度（摄氏度）：240电源：-4.5 V
Prop。Delay @ Nom-Sup：0.78 ns传播延迟（tpd）：0.73 ns
认证状态：Not QualifiedSame Edge Skew-Max（tskwd）：0.05 ns
座面最大高度：4.57 mm子类别：Clock Drivers
表面贴装：YES技术：ECL
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn85Pb15)
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：11.48 mmBase Number Matches：1

SY100E111AJI 数据手册

 浏览型号SY100E111AJI的Datasheet PDF文件第2页浏览型号SY100E111AJI的Datasheet PDF文件第3页浏览型号SY100E111AJI的Datasheet PDF文件第4页浏览型号SY100E111AJI的Datasheet PDF文件第5页 
ClockWorks™  
SY10E111A/L  
SY100E111A/L  
5V/3.3V 1:9 DIFFERENTIAL  
CLOCK DRIVER (w/o ENABLE)  
FEATURES  
DESCRIPTION  
■ 5V and 3.3V power supply options  
■ 200ps part-to-part skew  
The SY10/100E111A/L are low skew 1-to-9 differential  
driver designed for clock distribution in mind. The SY10/  
100E111A/L's function and performance are similar to the  
popular SY10/100E111, with the improvement of lower  
jitter and the added feature of low voltage operation. It  
accepts one signal input, which can be either differential or  
single-ended if the VBB output is used. The signal is fanned  
out to 9 identical differential outputs.  
The E111A/L are specifically designed, modeled and  
produced with low skew as the key goal. Optimal design  
and layout serve to minimize gate to gate skew within a  
device, andempiricalmodelingisusedtodetermineprocess  
control limits that ensure consistent tpd distributions from  
lot to lot. The net result is a dependable, guaranteed low  
skew device.  
■ 50ps output-to-output skew  
■ Differential design  
■ VBB output  
■ Voltage and temperature compensated outputs  
■ 75KΩ input pulldown resistors  
■ Fully compatible with Motorola MC100LVE111  
■ Available in 28-pin PLCC package  
BLOCK DIAGRAM  
To ensure that the tight skew specification is met it is  
necessary that both sides of the differential output are  
terminated into 50Ω, even if only one side is being used. In  
most applications, all nine differential pairs will be used and  
therefore terminated. In the case where fewer that nine  
pairs are used, it is necessary to terminate at least the  
output pairs on the same package side as the pair(s) being  
used on that side, in order to maintain minimum skew.  
Failure to do this will result in small degradations of  
propagation delay (on the order of 10-20ps) of the output(s)  
being used which, while not being catastrophic to most  
designs, will mean a loss of skew margin.  
The E111A/L, as with most other ECL devices, can be  
operated from a positive VCC supply in PECL mode. This  
allows the E111A/L to be used for high performance clock  
distribution in +5V/+3.3V systems. Designers can take  
advantage of the E111A/L's performance to distribute low  
skew clocks across the backplane or the board. In a PECL  
environment, series or Thevenin line terminations are  
typically used as they require no additional power supplies.  
For systems incorporating GTL, parallel termination offers  
the lowest power by taking advantage of the 1.2V supply as  
terminating voltage.  
Q
Q
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0
1
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IN  
IN  
V
BB  
Rev.: F  
Amendment: /0  
Rev. Date: October, 1998  
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SY100E111JCJC MICROCHIP

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