SY100E111JY

更新时间： 2024-11-07 05:04:31

品牌	Logo	应用领域
麦瑞 - MICREL		时钟驱动器逻辑集成电路
页数	文件大小	规格书
4页	68K
描述
1:9 DIFFERENTIAL CLOCK DRIVER WITH ENABLE

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SY100E111JY 数据手册

SY10E111

Micrel, Inc.

SY100E111

1:9 DIFFERENTIAL CLOCK

DRIVER WITH ENABLE

SY10E111

SY100E111

FEATURES

DESCRIPTION

■ Low skew

The SY10/100E111 are low skew 1-to-9 differential

drivers designed for clock distribution in new, high-

performance ECL systems. They accept one differential or

single-ended input, with V_BBused for single-ended

operation. The signal is fanned out to nine identical

differential outputs. An enable input is also provided such

that a logic HIGH disables the device by forcing all Q

outputs LOW and all /Q outputs HIGH.

■ Extended 100E V_EErange of –4.2V to –5.5V

■ Guaranteed skew limits

■ Differential design

■ V_BBoutput

■ Enable input

■ Fully compatible with industry standard 10KH, 100K

The device is specifically designed and produced for low

skew. The interconnect scheme and metal layout are

carefully optimized for minimal gate-to-gate skew within

the device. Wafer characterization and process control

ensure consistent distribution of propagation delay from lot

to lot. Since the E111 shares a common set of “basic”

processing with the other members of the ECLinPS™

family, wafer characterization at the point of device

personalization allows for tighter control of parameters,

including propagation delay.

I/O levels

■ 75KΩ input pulldown resistors

■ Fully compatible with ON Semiconductor

MC10E/100E111

■ Available in 28-pin PLCC package

BLOCK DIAGRAM

To ensure that the skew specification is met, it is

necessary that both sides of the differential output are

terminated into 50Ω, even if only one side is being used. ln

most applications, all nine differential pairs will be used

and, therefore, terminated. In the case where fewer than

nine pairs are used, it is necessary to terminate at least the

output pairs on the same package side (i.e. sharing the

same V_CCOas the pair(s) being used on that side) in order

to maintain minimum skew.

The V_BBoutput is intended for use as a reference

voltage for single-ended reception of ECL signals to that

device only. When using V_BBfor this purpose, it is

recommended that V_BBis decoupled to V_CCvia a 0.01µF

capacitor.

PIN NAMES

Function

Differential Input Pair

Enable Input

IN, /IN

/EN

Q0, /Q0 — Q8, /Q8

Differential Outputs

V_BBOutput

V_BB

V_CCO

V_CCto Output

VBB

Rev.: E

Amendment: /0

M9999-032006

hbwhelp@micrel.com or (408) 955-1690

Issue Date: March 2006

12 3 4

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与SY100E111JY相关器件

型号	品牌	获取价格	描述	数据表
SY100E111JYTR	MICREL	获取价格	1:9 DIFFERENTIAL CLOCK DRIVER WITH ENABLE
SY100E111LE	MICREL	获取价格	5V/3.3V 1:9 DIFFERENTIAL CLOCK DRIVER (w/ENABLE)
SY100E111LEJC	MICREL	获取价格	5V/3.3V 1:9 DIFFERENTIAL CLOCK DRIVER (w/ENABLE)
SY100E111LEJCTR	MICREL	获取价格	5V/3.3V 1:9 DIFFERENTIAL CLOCK DRIVER (w/ENABLE)
SY100E111LEJCTR	MICROCHIP	获取价格	Low Skew Clock Driver, 100E Series, 9 True Output(s), 0 Inverted Output(s), ECL, PQCC28, P
SY100E111LEJI	MICREL	获取价格	5V/3.3V 1:9 DIFFERENTIAL CLOCK DRIVER (w/ENABLE)
SY100E111LEJITR	MICREL	获取价格	5V/3.3V 1:9 DIFFERENTIAL CLOCK DRIVER (w/ENABLE)
SY100E111LEJITR	MICROCHIP	获取价格	Low Skew Clock Driver, 100E Series, 9 True Output(s), 0 Inverted Output(s), ECL, PQCC28, P
SY100E111LEJY	MICREL	获取价格	5V/3.3V 1:9 DIFFERENTIAL CLOCK DRIVER (w/ENABLE)
SY100E111LEJYTR	MICROCHIP	获取价格	100E SERIES, LOW SKEW CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC28, LEAD F

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