5秒后页面跳转
捷配首页

Datasheet > 逻辑 > 时钟驱动器> SY100E111LEJI
SY100E111LEJI PDF预览

SY100E111LEJI

更新时间： 2024-11-06 22:31:23
品牌 Logo 应用领域
麦瑞 - MICREL 时钟驱动器逻辑集成电路
页数 文件大小 规格书
6页 93K
描述
5V/3.3V 1:9 DIFFERENTIAL CLOCK DRIVER (w/ENABLE)

阅读下载

中文翻译

获取价格

SY100E111LEJI 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：PLASTIC, LCC-28Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01风险等级：5.04
系列：100E输入调节：DIFFERENTIAL
JESD-30 代码：S-PQCC-J28JESD-609代码：e0
长度：11.48 mm逻辑集成电路类型：LOW SKEW CLOCK DRIVER
湿度敏感等级：1功能数量：1
反相输出次数：端子数量：28
实输出次数：9最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装等效代码：LDCC28,.5SQ
封装形状：SQUARE封装形式：CHIP CARRIER
峰值回流温度（摄氏度）：240电源：-3.3 V
Prop。Delay @ Nom-Sup：0.73 ns传播延迟（tpd）：0.73 ns
认证状态：Not QualifiedSame Edge Skew-Max（tskwd）：0.05 ns
座面最大高度：4.37 mm子类别：Clock Drivers
最大供电电压 (Vsup)：3.8 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：ECL温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn85Pb15)端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30宽度：11.48 mm
Base Number Matches：1

SY100E111LEJI 数据手册

 浏览型号SY100E111LEJI的Datasheet PDF文件第2页浏览型号SY100E111LEJI的Datasheet PDF文件第3页浏览型号SY100E111LEJI的Datasheet PDF文件第4页浏览型号SY100E111LEJI的Datasheet PDF文件第5页浏览型号SY100E111LEJI的Datasheet PDF文件第6页 
ClockWorks™  
SY10E111AE/LE  
SY100E111AE/LE  
5V/3.3V 1:9 DIFFERENTIAL  
CLOCK DRIVER (w/ENABLE)  
FEATURES  
DESCRIPTION  
■ 5V and 3.3V power supply options  
■ 200ps part-to-part skew  
TheSY10/100E111AE/LEarelowskew1-to-9differential  
drivers designed for clock distribution in mind. The SY10/  
100E111AE/LE's function and performance are similar to  
the popular SY10/100E111, with the improvement of lower  
jitter and the added feature of low voltage operation. It  
accepts one signal input, which can be either differential or  
single-ended if the VBB output is used. The signal is fanned  
out to 9 identical differential outputs. An enable input is  
also provided such that a logic HIGH disables the device by  
forcing all Q outputs LOW and all Q outputs HIGH.  
The E111AE/LE is specifically designed, modeled and  
produced with low skew as the key goal. Optimal design  
and layout serve to minimize gate to gate skew within a  
device, andempiricalmodelingisusedtodetermineprocess  
control limits that ensure consistent tpd distributions from  
lot to lot. The net result is a dependable, guaranteed low  
skew device.  
■ 50ps output-to-output skew  
■ Differential design  
■ VBB output  
■ Enable Input  
■ Voltage and temperature compensated outputs  
■ 75KΩ input pulldown resistors  
■ Fully compatible with Motorola MC10/100E111  
■ Available in 28-pin PLCC package  
BLOCK DIAGRAM  
To ensure that the tight skew specification is met it is  
necessary that both sides of the differential output are  
terminated into 50Ω, even if only one side is being used. In  
most applications, all nine differential pairs will be used  
and therefore terminated. In the case where fewer that  
nine pairs are used, it is necessary to terminate at least the  
output pairs on the same package side as the pair(s) being  
used on that side, in order to maintain minimum skew.  
Failure to do this will result in small degradations of  
propagation delay (on the order of 10-20ps) of the output(s)  
being used which, while not being catastrophic to most  
designs, will mean a loss of skew margin.  
The E111AE/LE, as with most other ECL devices, can  
be operated from a positive VCC supply in PECL mode.  
This allows the E111AE/LE to be used for high performance  
clock distribution in +5V/+3.3V systems. Designers can  
take advantage of the E111AE/LE's performance to  
distribute low skew clocks across the backplane or the  
board. In a PECL environment, series or Thevenin line  
terminations are typically used as they require no additional  
power supplies. For systems incorporating GTL, parallel  
termination offers the lowest power by taking advantage of  
the 1.2V supply as terminating voltage.  
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
0
0
1
1
2
2
3
3
4
4
5
IN  
IN  
EN  
Q
Q
5
6
Q
Q
Q
Q
Q
6
7
7
8
8
VBB  
Rev.: D  
Amendment: /0  
Rev. Date: October, 1998  
1
123456

中文翻译

下载PDF

与SY100E111LEJI相关器件

型号 品牌 获取价格 描述 数据表
SY100E111LEJITR MICREL

获取价格

 		5V/3.3V 1:9 DIFFERENTIAL CLOCK DRIVER (w/ENABLE)
SY100E111LEJITR MICROCHIP

获取价格

 		Low Skew Clock Driver, 100E Series, 9 True Output(s), 0 Inverted Output(s), ECL, PQCC28, P
SY100E111LEJY MICREL

获取价格

 		5V/3.3V 1:9 DIFFERENTIAL CLOCK DRIVER (w/ENABLE)
SY100E111LEJYTR MICROCHIP

获取价格

 		100E SERIES, LOW SKEW CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC28, LEAD F
SY100E111LEJYTR MICREL

获取价格

 		5V/3.3V 1:9 DIFFERENTIAL CLOCK DRIVER (w/ENABLE)
SY100E111LEJZ MICREL

获取价格

 		5V/3.3V 1:9 DIFFERENTIAL CLOCK DRIVER
SY100E111LEJZTR MICREL

获取价格

 		5V/3.3V 1:9 DIFFERENTIAL CLOCK DRIVER
SY100E111LEJZTR MICROCHIP

获取价格

 		100E SERIES, LOW SKEW CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC28, LEAD F
SY100E111LEJZ-TR MICROCHIP

获取价格

 		100E SERIES, LOW SKEW CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC28
SY100E111LJC MICREL

获取价格

 		5V/3.3V 1:9 DIFFERENTIAL CLOCK DRIVER w/o ENABLE

与SY100E111LEJI相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证