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SY100E111AJITR

更新时间： 2024-09-17 18:35:27
品牌 Logo 应用领域
美国微芯 - MICROCHIP 驱动逻辑集成电路
页数 文件大小 规格书
6页 73K
描述
Low Skew Clock Driver, 100E Series, 9 True Output(s), 0 Inverted Output(s), ECL, PQCC28, PLASTIC, LCC-28

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SY100E111AJITR 技术参数

生命周期：Not Recommended包装说明：QCCJ,
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.06系列：100E
输入调节：DIFFERENTIALJESD-30 代码：S-PQCC-J28
长度：11.48 mm逻辑集成电路类型：LOW SKEW CLOCK DRIVER
功能数量：1反相输出次数：
端子数量：28实输出次数：18
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装形状：SQUARE封装形式：CHIP CARRIER
传播延迟（tpd）：0.78 nsSame Edge Skew-Max（tskwd）：0.075 ns
座面最大高度：4.57 mm表面贴装：YES
技术：ECL温度等级：INDUSTRIAL
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD宽度：11.48 mm
Base Number Matches：1

SY100E111AJITR 数据手册

 浏览型号SY100E111AJITR的Datasheet PDF文件第2页浏览型号SY100E111AJITR的Datasheet PDF文件第3页浏览型号SY100E111AJITR的Datasheet PDF文件第4页浏览型号SY100E111AJITR的Datasheet PDF文件第5页浏览型号SY100E111AJITR的Datasheet PDF文件第6页 
®
Precision Edge  
5V/3.3V 1:9 DIFFERENTIAL  
CLOCK DRIVER (w/o ENABLE)  
SY10E111A/L  
SY100E111A/L  
FEATURES  
■ 5V and 3.3V power supply options  
■ 200ps part-to-part skew  
®
Precision Edge  
■ 50ps output-to-output skew  
■ Differential design  
DESCRIPTION  
■ VBB output  
The SY10/100E111A/L are low skew 1-to-9 differential  
driver designed for clock distribution in mind. The  
SY10/100E111A/L's function and performance are similar to  
the popular SY10/100E111, with the improvement of lower  
jitterandtheaddedfeatureoflowvoltageoperation. Itaccepts  
one signal input, which can be either differential or single-  
ended if the VBB output is used. The signal is fanned out to 9  
identical differential outputs.  
■ Voltage and temperature compensated outputs  
■ 75KΩ input pulldown resistors  
■ Fully compatible with Motorola MC100LVE111  
■ Available in 28-pin PLCC package  
BLOCK DIAGRAM  
The E111A/L are specifically designed, modeled and  
produced with low skew as the key goal. Optimal design and  
layoutservetominimizegatetogateskewwithinadevice,and  
empirical modeling is used to determine process control limits  
that ensure consistent tpd distributions from lot to lot. The net  
result is a dependable, guaranteed low skew device.  
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
To ensure that the tight skew specification is met it is  
necessary that both sides of the differential output are  
terminated into 50Ω, even if only one side is being used. In  
most applications, all nine differential pairs will be used and  
therefore terminated. In the case where fewer that nine pairs  
are used, it is necessary to terminate at least the output pairs  
on the same package side as the pair(s) being used on that  
side, in order to maintain minimum skew. Failure to do this will  
resultinsmalldegradationsofpropagationdelay(ontheorder  
of 10-20ps) of the output(s) being used which, while not being  
catastrophictomostdesigns, willmeanalossofskewmargin.  
IN  
IN  
The E111A/L, as with most other ECL devices, can be  
operated from a positive VCC supply in PECL mode. This  
allows the E111A/L to be used for high performance clock  
distribution in +5V/+3.3V systems. Designers can take  
advantage of the E111A/L's performance to distribute low  
skew clocks across the backplane or the board. In a PECL  
environment,seriesorTheveninlineterminationsaretypically  
used as they require no additional power supplies. For  
systems incorporating GTL, parallel termination offers the  
lowest power by taking advantage of the 1.2V supply as  
terminating voltage.  
V
BB  
PIN NAMES  
Pin  
IN, IN  
Function  
Differential Input Pair  
Differential Outputs  
VBB Output  
Q0, Q0 — Q8, Q8  
VBB  
VCCO  
VCC to Output  
Precision Edge is a registered trademark of Micrel, Inc.  
Rev.: J  
Amendment: /0  
M9999-032006  
hbwhelp@micrel.com or (408) 955-1690  
1
Rev. Date: March 2006  
123456

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