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SY100E111JITR

更新时间： 2024-09-17 05:04:31
品牌 Logo 应用领域
麦瑞 - MICREL 时钟驱动器逻辑集成电路
页数 文件大小 规格书
4页 68K
描述
1:9 DIFFERENTIAL CLOCK DRIVER WITH ENABLE

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中文翻译

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SY100E111JITR 技术参数

是否Rohs认证： 不符合生命周期：Transferred
零件包装代码：QLCC包装说明：QCCJ, LDCC28,.5SQ
针数：28Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01风险等级：5.06
系列：100E输入调节：DIFFERENTIAL
JESD-30 代码：S-PQCC-J28JESD-609代码：e0
长度：11.48 mm逻辑集成电路类型：LOW SKEW CLOCK DRIVER
湿度敏感等级：1功能数量：1
反相输出次数：端子数量：28
实输出次数：9最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装等效代码：LDCC28,.5SQ
封装形状：SQUARE封装形式：CHIP CARRIER
峰值回流温度（摄氏度）：240电源：-4.5 V
Prop。Delay @ Nom-Sup：0.73 ns传播延迟（tpd）：0.73 ns
认证状态：Not QualifiedSame Edge Skew-Max（tskwd）：0.05 ns
座面最大高度：4.57 mm子类别：Clock Drivers
表面贴装：YES技术：ECL
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn85Pb15)
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：11.48 mmBase Number Matches：1

SY100E111JITR 数据手册

 浏览型号SY100E111JITR的Datasheet PDF文件第2页浏览型号SY100E111JITR的Datasheet PDF文件第3页浏览型号SY100E111JITR的Datasheet PDF文件第4页 
1:9 DIFFERENTIAL CLOCK  
DRIVER WITH ENABLE  
SY10E111  
SY100E111  
FEATURES  
DESCRIPTION  
■ Low skew  
The SY10/100E111 are low skew 1-to-9 differential  
drivers designed for clock distribution in new, high-  
performance ECL systems. They accept one differential or  
single-ended input, with VBB used for single-ended  
operation. The signal is fanned out to nine identical  
differential outputs. An enable input is also provided such  
that a logic HIGH disables the device by forcing all Q  
outputs LOW and all /Q outputs HIGH.  
■ Extended 100E VEE range of –4.2V to –5.5V  
■ Guaranteed skew limits  
■ Differential design  
■ VBB output  
■ Enable input  
■ Fully compatible with industry standard 10KH, 100K  
The device is specifically designed and produced for low  
skew. The interconnect scheme and metal layout are  
carefully optimized for minimal gate-to-gate skew within  
the device. Wafer characterization and process control  
ensure consistent distribution of propagation delay from lot  
to lot. Since the E111 shares a common set of “basic”  
processing with the other members of the ECLinPS™  
family, wafer characterization at the point of device  
personalization allows for tighter control of parameters,  
including propagation delay.  
I/O levels  
■ 75KΩ input pulldown resistors  
■ Fully compatible with ON Semiconductor  
MC10E/100E111  
■ Available in 28-pin PLCC package  
BLOCK DIAGRAM  
To ensure that the skew specification is met, it is  
necessary that both sides of the differential output are  
terminated into 50Ω, even if only one side is being used. ln  
most applications, all nine differential pairs will be used  
and, therefore, terminated. In the case where fewer than  
nine pairs are used, it is necessary to terminate at least the  
output pairs on the same package side (i.e. sharing the  
same VCCO as the pair(s) being used on that side) in order  
to maintain minimum skew.  
The VBB output is intended for use as a reference  
voltage for single-ended reception of ECL signals to that  
device only. When using VBB for this purpose, it is  
recommended that VBB is decoupled to VCC via a 0.01µF  
capacitor.  
Q0  
Q0  
Q1  
Q1  
Q2  
Q2  
Q3  
Q3  
IN  
IN  
Q4  
Q4  
Q5  
Q5  
Q6  
Q6  
Q7  
Q7  
Q8  
Q8  
EN  
PIN NAMES  
Pin  
Function  
Differential Input Pair  
Enable Input  
IN, /IN  
/EN  
Q0, /Q0 — Q8, /Q8  
Differential Outputs  
VBB Output  
VBB  
VCCO  
VCC to Output  
VBB  
Rev.: E  
Amendment: /0  
M9999-032006  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: March 2006  
1234

中文翻译

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