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SY100E111AEJY

更新时间： 2024-11-07 05:04:31
品牌 Logo 应用领域
麦瑞 - MICREL 时钟驱动器逻辑集成电路
页数 文件大小 规格书
6页 78K
描述
5V/3.3V 1:9 DIFFERENTIAL CLOCK DRIVER (w/ENABLE)

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SY100E111AEJY 数据手册

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Precision Edge®  
5V/3.3V 1:9 DIFFERENTIAL  
CLOCK DRIVER (w/ENABLE)  
SY10E111AE/LE  
SY100E111AE/LE  
FEATURES  
■ 5V and 3.3V power supply options  
■ 200ps part-to-part skew  
®
Precision Edge  
■ 50ps output-to-output skew  
■ Differential design  
DESCRIPTION  
■ VBB output  
TheSY10/100E111AE/LEarelowskew1-to-9differential  
drivers designed for clock distribution in mind. The SY10/  
100E111AE/LE's function and performance are similar to  
the popular SY10/100E111, with the improvement of lower  
jitter and the added feature of low voltage operation. It  
accepts one signal input, which can be either differential or  
single-ended if the VBB output is used. The signal is fanned  
out to 9 identical differential outputs. An enable input is  
also provided such that a logic HIGH disables the device by  
forcing all Q outputs LOW and all Q outputs HIGH.  
The E111AE/LE is specifically designed, modeled and  
produced with low skew as the key goal. Optimal design  
and layout serve to minimize gate to gate skew within a  
device, andempiricalmodelingisusedtodetermineprocess  
control limits that ensure consistent tpd distributions from  
lot to lot. The net result is a dependable, guaranteed low  
skew device.  
To ensure that the tight skew specification is met it is  
necessary that both sides of the differential output are  
terminated into 50Ω, even if only one side is being used. In  
most applications, all nine differential pairs will be used  
and therefore terminated. In the case where fewer that  
nine pairs are used, it is necessary to terminate at least the  
output pairs on the same package side as the pair(s) being  
used on that side, in order to maintain minimum skew.  
Failure to do this will result in small degradations of  
propagation delay (on the order of 10-20ps) of the output(s)  
being used which, while not being catastrophic to most  
designs, will mean a loss of skew margin.  
■ Enable Input  
■ Voltage and temperature compensated outputs  
■ 75KΩ input pulldown resistors  
■ Fully compatible with Motorola MC10/100E111  
■ Available in 28-pin PLCC package  
BLOCK DIAGRAM  
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
0
0
1
1
2
2
3
3
4
4
5
IN  
IN  
EN  
Q
Q
5
6
Q
Q
Q
Q
Q
6
7
7
8
8
The E111AE/LE, as with most other ECL devices, can  
be operated from a positive VCC supply in PECL mode.  
This allows the E111AE/LE to be used for high performance  
clock distribution in +5V/+3.3V systems. Designers can  
take advantage of the E111AE/LE's performance to  
distribute low skew clocks across the backplane or the  
board. In a PECL environment, series or Thevenin line  
terminations are typically used as they require no additional  
power supplies. For systems incorporating GTL, parallel  
termination offers the lowest power by taking advantage of  
the 1.2V supply as terminating voltage.  
V
BB  
PIN NAMES  
Pin  
IN, IN  
Function  
Differential Input Pair  
Enable Input  
EN  
Q0, Q0 — Q8, Q8  
VBB  
Differential Outputs  
VBB Output  
VCCO  
VCC to Output  
Precision Edge is a registered trademark of Micrel, Inc.  
Rev.: G  
Amendment: /0  
M9999-032006  
hbwhelp@micrel.com or (408) 955-1690  
1
Rev. Date: March 2006  
123456

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SY100E111AEJY 替代型号

型号 品牌 替代类型 描述 数据表
SY100E111LJY MICROCHIP

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