Datasheet > STP1081ABGA-125

STP1081ABGA-125

更新时间： 2024-09-13 23:35:19

品牌	Logo	应用领域
其他 - ETC		/
页数	文件大小	规格书
32页	363K
描述
Address/Data Buffer

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STP1081ABGA-125 数据手册

STP1081

July 1997

UltraSPARC^™-II Data Buffer (UDB-II)

Companion Device for 250/ 300 MHz UltraSPARC-II Systems

DATA SHEET

DESCRIPTION

The UltraSPARC-II Data Buffer (UDB-II) consists of two identical ASICs connecting the UltraSPARC-II micro-

processor and its E-Cache to the system data bus (i.e., UPA bus). These two are designated UDB_H (for the

most-signiﬁcant data bits) and UDB_L (for the least-signiﬁcant data bits). The UDB-II moves data between the

E-Cache bus and the UPA data bus (see Figure 1), enabling the system to send data to and receive data from

the faster CPU transparently. The E-Cache bus has 128 data bits and 16 parity bits, for a total width of 144 bits.

The data bus is also 144 bits wide, including 128 data bits and 16 error-correction code (ECC) bits. Noncache-

able loads and stores use the E-Cache bus for moving data to the data buffer located in UDB_H and UDB_L.

The UDB-II (model STP1081ABGA) is built with leading-edge CMOS ASIC technology featuring 0.5-micron

geometries, and a three-layer metal process. It operates at 2.6 V and 3.3 V.

Features

Beneﬁts

• Isolates the processor from the system bus

• Interface to the UPA

• High performance: ease of design

• Fully synchronous design

• Operates at system frequency

• Operates at half the processor frequency

• Provides data buffering

• Supports parity on the CPU side and ECC on the system

side

• Stores interrupt vectors. Interrupt registers visible to

software

• Enables secondary cache transfers and system memory

transfers by isolation

• IEEE standard 1149.1 (JTAG) boundary scan test

• 256 PBGA package

• Ease of manufacturing test

• Small footprint and cost effective packaging

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