Datasheet > STD419S

STD419S

更新时间： 2024-01-24 06:17:52

品牌	Logo	应用领域
三合微科 - SAMHOP		晶体晶体管
页数	文件大小	规格书
8页	379K
描述
P-Channel Logic Level EnhancementMode Field E ffect Transistor

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中文翻译

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技术参数
数据手册

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STD419S 技术参数

生命周期：	Contact Manufacturer	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.61
Base Number Matches：	1

STD419S 数据手册

S TU/D419S

S amHop Microelectronics C orp.

Mar,29, 2007

P -C hannel Logic Level E nhancement Mode Field E ffect Transistor

FE ATUR E S

PR ODUCT S UMMAR Y

S uper high dense cell design for low R DS (ON).

R DS (ON) ( m

)

Max

Ω

VDS S

R ugged and reliable.

@ VG S = -10V

S urface Mount P ackage.

E S D P rocteced

-40A

-40V

12 @ VG S = -4.5V

S TU S E R IE S

TO-252AA(D-P AK)

S TD S E R IE S

TO-251(l-P AK)

AB S OL UTE MAXIMUM R ATING S

=25 C unles s otherwis e noted)

Unit

Limit

-40

P arameter

S ymbol

Drain-S ource Voltage

G S

G ate-S ource Voltage

25 C

-40

-32

Drain C urrent-C ontinuous @ Ta

70 C

-P ulsed ^b

-100

-10

Drain-S ource Diode Forward C urrent ^a

Ta= 25 C

Maximum P ower Dissipation ^a

Ta=70 C

Operating J unction and S torage

Temperature R ange

-55 to 175

TJ , TS TG

THE R MAL C HAR AC TE R IS TIC S

Thermal R esistance, J unction-to-C ase

C/W

J C

J A

Thermal R esistance, J unction-to-Ambient

12 3 4 5 6 7 8

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