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SST25WF080

更新时间： 2024-11-23 06:14:23
品牌 Logo 应用领域
SST 闪存
页数 文件大小 规格书
29页 838K
描述
8Mbit 1.8V SPI Serial Flash

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中文翻译

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SST25WF080 数据手册

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8Mbit 1.8V SPI Serial Flash  
SST25WF080  
SST25VF016B16Mb Serial Peripheral Interface (SPI) flash memory  
Advance Information  
FEATURES:  
•
•
•
•
Single Voltage Read and Write Operations  
– 1.65-1.95V  
Serial Interface Architecture  
– SPI Compatible: Mode 0 and Mode 3  
High Speed Clock Frequency  
– 75 MHz  
•
•
End-of-Write Detection  
– Software polling the BUSY bit in Status Register  
– Busy Status readout on SO pin  
Reset Pin (RST#) or Programmable Hold Pin  
(HOLD#) option  
– Hardware Reset pin as default  
– Hold pin option to suspend a serial sequence  
without deselecting the device  
Superior Reliability  
– Endurance: 100,000 Cycles (typical)  
– Greater than 100 years Data Retention  
•
•
Write Protection (WP#)  
– Enables/Disables the Lock-Down function of the  
status register  
Software Write Protection  
– Write protection through Block-Protection bits in  
status register  
•
•
Ultra-Low Power Consumption:  
– Active Read Current: 2 mA (typical @ 33 MHz)  
– Standby Current: 5 µA (typical)  
Flexible Erase Capability  
– Uniform 4 KByte sectors  
– Uniform 32 KByte overlay blocks  
– Uniform 64 KByte overlay blocks  
Fast Erase and Byte-Program:  
– Chip-Erase Time: 35 ms (typical)  
•
•
Temperature Range  
– Industrial: -40°C to +85°C  
Packages Available  
– 8-lead SOIC (150 mils)  
– 8-bump XFBGA  
All devices are RoHS compliant  
•
•
– Sector-/Block-Erase Time: 18 ms (typical)  
– Byte-Program Time: 14 µS (typical)  
•
Auto Address Increment (AAI) Programming  
– Decrease total chip programming time over  
Byte-Program operations  
PRODUCT DESCRIPTION  
The SST25WF080 is a member of the Serial Flash 25  
Series family and features a four-wire, SPI-compatible  
interface that allows for a low pin-count package which  
occupies less board space and ultimately lowers total sys-  
tem costs. SST25WF080 SPI serial flash memory is manu-  
factured with SST proprietary, high-performance CMOS  
SuperFlash technology. The split-gate cell design and  
thick-oxide tunneling injector attain better reliability and  
manufacturability compared with alternate approaches.  
1.65-1.95V for SST25WF080. The total energy consumed  
is a function of the applied voltage, current, and time of  
application. Since for any given voltage range, the Super-  
Flash technology uses less current to program and has a  
shorter erase time, the total energy consumed during any  
Erase or Program operation is less than alternative flash  
memory technologies.  
The SST25WF080 is offered in both an 8-lead, 150 mils  
SOIC package and an 8-bump XFBGA package. See Fig-  
ures 2 and 3 for the pin assignments.  
The SST25WF080 significantly improves performance and  
reliability, while lowering power consumption. The device  
writes (Program or Erase) with a single power supply of  
©2010 Silicon Storage Technology, Inc.  
The SST logo and SuperFlash are registered Trademarks of Silicon Storage Technology, Inc.  
These specifications are subject to change without notice.  
S71203-03-000  
1
04/10  
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