SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759B – OCTOBER 2002 – REVISED APRIL 2003
Members of the Texas Instruments (TI)
Family of JTAG Scan-Support Products
Bypass (BYP –BYP ) Forces Primary to
5 0
Configured Secondary Paths Without Use
of Linking Shadow Protocols
Extend Scan Access From Board Level to
Higher Level of System Integration
Connect (CON –CON ) Provides Indication
2
0
of Primary-to-Secondary Paths
Connections
Three IEEE Std 1149.1-Compatible
Configurable Secondary Scan Paths to One
Primary Scan Path
Secondary TAPs Can Be Configured at
High Impedance Via the OE Input to Allow
an Alternate Test Master to Take Control of
the Secondary TAPs
Multiple Devices Can Be Cascaded to Link
24 Secondary Scan Paths to One Primary
Scan Path
High-Drive Outputs (–32 mA I , 64 mA I
OH
)
OL
Simple (Linking Shadow) Protocol Is Used
to Connect the Primary Test Access Port
(TAP) to Secondary TAPs. This Single
Protocol Is Used to Address and Configure
the Secondary Scan Path.
Support Backplane Interface at Primary
Outputs and High Fanout at Secondary
Outputs
While Powered at 3.3 V, Both the Primary
and Secondary TAPs Are Fully 5-V Tolerant
for Interfacing 5-V and/or 3.3-V Masters and
Targets
The LASP(8986) and ASP(8996) Can Be
Configured on the Same Backplane Using
Similar Shadow Protocols
Package Options Include Plastic BGA
(GGV) and LQFP (PM) Packages and
Ceramic Quad Flat (HV) Packages Using
25-mil Center-to-Center Spacing
Linking Shadow Protocols Can Occur in
Any of Test-Logic-Reset, Run-Test/Idle,
Pause-DR, Pause-IR TAP States to Provide
Board-to-Board and Built-In Self-Test
description/ordering information
The ’LVT8986 Linking Addressable Scan Ports (LASPs) are members of the Texas Instruments family of IEEE
Std 1149.1 (JTAG) scan-support products. The scan-support product family facilitates testing of fully
boundary-scannable devices. The LASP applies linking shadow protocols through the test access port (TAP)
to extend scan access to the system level and divide scan chains at the board level.
The LASP consists of a primary TAP for interfacing to the backplane IEEE Std 1149.1 serial-bus signals (PTDI,
PTMS, PTCK, PTDO, PRTST) and three secondary TAPs for interfacing to the board-level IEEE Std 1149.1
serial-bus signals. Each secondary TAP consists of signals STDI , STMS , STCK , STDO , and STRST .
x
x
x
x
x
Conceptually, the LASP is a simple switch that can be used to connect directly a set of primary TAP signals to
a set of secondary TAP signals—for example, to interface backplane TAP signals to a board-level TAP. The
LASP provides all signal buffering that might be required at these two interfaces. Primary-to-secondary TAP
connectionscan be configured with the help of linking shadow protocol or protocol bypass (BYP –BYP ) inputs.
5
0
All possible configurations are tabulated in Function Tables 1, 2, and 3.
ORDERING INFORMATION
ORDERABLE
TOP-SIDE
MARKING
†
PACKAGE
T
A
PART NUMBER
SN74LVT8986GGV
SN74LVT8986PM
PBGA (GGV)
LQFP – PM
CFP – HV
LVT8986
–40°C to 85°C
–55°C to 125°C
LVT8986
SNJ54LVT8986HV
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB
design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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