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SN74V3690-7PEU PDF预览

SN74V3690-7PEU

更新时间： 2024-11-21 04:31:15
品牌 Logo 应用领域
德州仪器 - TI 存储内存集成电路先进先出芯片时钟
页数 文件大小 规格书
50页 725K
描述
1024 】 36, 2048 】 36, 4096 】 36, 8192 】 36, 16384 】 36, 32768 】 36 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES

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SN74V3690-7PEU 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：QFP
包装说明：PLASTIC, LQFP-128针数：128
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.32.00.71Factory Lead Time：1 week
风险等级：5.29Is Samacsys：N
最长访问时间：5 ns最大时钟频率 (fCLK)：133.3 MHz
周期时间：7.5 nsJESD-30 代码：R-PQFP-G128
JESD-609代码：e4长度：20 mm
内存密度：1179648 bit内存集成电路类型：OTHER FIFO
内存宽度：36湿度敏感等级：3
功能数量：1端子数量：128
字数：32768 words字数代码：32000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：32KX36
可输出：YES封装主体材料：PLASTIC/EPOXY
封装代码：LFQFP封装等效代码：QFP128,.63X.87,20
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE, FINE PITCH
并行/串行：PARALLEL峰值回流温度（摄氏度）：220
电源：3.3 V认证状态：Not Qualified
座面最大高度：1.6 mm子类别：FIFOs
最大压摆率：0.04 mA最大供电电压 (Vsup)：3.45 V
最小供电电压 (Vsup)：3.15 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mmBase Number Matches：1

SN74V3690-7PEU 数据手册

 浏览型号SN74V3690-7PEU的Datasheet PDF文件第2页浏览型号SN74V3690-7PEU的Datasheet PDF文件第3页浏览型号SN74V3690-7PEU的Datasheet PDF文件第4页浏览型号SN74V3690-7PEU的Datasheet PDF文件第5页浏览型号SN74V3690-7PEU的Datasheet PDF文件第6页浏览型号SN74V3690-7PEU的Datasheet PDF文件第7页 
SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690  
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36  
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES  
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003  
Choice of Memory Organizations  
Empty, Full, and Half-Full Flags Signal FIFO  
Status  
– SN74V3640 – 1024 × 36 Bit  
– SN74V3650 – 2048 × 36 Bit  
– SN74V3660 – 4096 × 36 Bit  
– SN74V3670 – 8192 × 36 Bit  
– SN74V3680 – 16384 × 36 Bit  
– SN74V3690 – 32768 × 36 Bit  
Programmable Almost-Empty and  
Almost-Full Flags; Each Flag Can Default to  
One of Eight Preselected Offsets  
Selectable Synchronous/Asynchronous  
Timing Modes for Almost-Empty and  
Almost-Full Flags  
166-MHz Operation (6-ns Read/Write Cycle  
Time)  
Program Programmable Flags by Either  
Serial or Parallel Means  
User-Selectable Input- and Output-Port Bus  
Sizing  
– ×36 in to ×36 out  
– ×36 in to ×18 out  
– ×36 in to ×9 out  
Select Standard Timing (Using EF and FF  
Flags) or First-Word Fall-Through (FWFT)  
Timing (Using OR and IR Flags)  
Output Enable Puts Data Outputs in  
High-Impedance State  
– ×18 in to ×36 out  
– ×9 in to ×36 out  
Easily Expandable in Depth and Width  
Big-Endian/Little-Endian User-Selectable  
Byte Representation  
Independent Read and Write Clocks Permit  
Reading and Writing Simultaneously  
5-V-Tolerant Inputs  
High-Performance Submicron CMOS  
Technology  
Fixed, Low, First-Word Latency  
Zero-Latency Retransmit  
Master Reset Clears Entire FIFO  
Available in 128-Pin Thin Quad Flat Pack  
(TQFP)  
Partial Reset Clears Data, But Retains  
Programmable Settings  
description  
The SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, and SN74V3690 are exceptionally  
deep, high-speed CMOS, first-in first-out (FIFO) memories, with clocked read and write controls and a flexible  
bus-matching ×36/×18/×9 data flow. These FIFOs offer several key user benefits:  
Flexible ×36/×18/×9 bus matching on both read and write ports  
The period required by the retransmit operation is fixed and short.  
The first-word data-latency period, from the time the first word is written to an empty FIFO to the time it can  
be read, is fixed and short.  
High-density offerings up to 1 Mbit  
Bus-matching synchronous FIFOs are particularly appropriate for network, video, signal processing,  
telecommunications, data communications, and other applications that need to buffer large amounts of data  
and match buses of unequal sizes.  
Each FIFO has a data input port (Dn) and a data output port (Qn), both of which can assume 36-bit, 18-bit, or  
9-bit width, as determined by the state of external control pins’ input width (IW), output width (OW), and bus  
matching (BM) during the master-reset cycle.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...50

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SN74V3690-7PEU 替代型号

型号 品牌 替代类型 描述 数据表
SN74V3690-6PEU TI

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 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES

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