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SN75061J PDF预览

SN75061J

更新时间: 2024-01-02 21:08:02
品牌 Logo 应用领域
德州仪器 - TI 驱动器
页数 文件大小 规格书
13页 212K
描述
IC,LAN TRANSCEIVER,SINGLE,BIPOLAR,DIP,16PIN,CERAMIC

SN75061J 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP16,.3Reach Compliance Code:not_compliant
风险等级:5.92数据速率:1000 Mbps
JESD-30 代码:R-XDIP-T16端子数量:16
收发器数量:1最高工作温度:70 °C
最低工作温度:封装主体材料:CERAMIC
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
认证状态:Not Qualified子类别:Network Interfaces
最大压摆率:70 mA表面贴装:NO
技术:BIPOLAR温度等级:COMMERCIAL
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUALBase Number Matches:1

SN75061J 数据手册

 浏览型号SN75061J的Datasheet PDF文件第2页浏览型号SN75061J的Datasheet PDF文件第3页浏览型号SN75061J的Datasheet PDF文件第4页浏览型号SN75061J的Datasheet PDF文件第5页浏览型号SN75061J的Datasheet PDF文件第6页浏览型号SN75061J的Datasheet PDF文件第7页 
ꢀ ꢁꢂ ꢃꢄ ꢅꢆ  
ꢇꢈꢉ ꢊꢋ ꢈꢌꢈꢋ ꢍꢋꢉ ꢊꢋꢈ ꢎꢏꢐꢉ ꢈꢎꢑ ꢉꢒ ꢓꢎ ꢀ ꢔꢕ ꢋ ꢖꢍ ꢓ  
SLLS026C − JANUARY 1987 − REVISED JULY 1990  
N PACKAGE  
(TOP VIEW)  
IEEE 802.3 1BASE5 Driver and Receiver  
On-Chip Receiver Squelch With Adjustable  
Threshold  
V
DRDLAJ  
DRO +  
DRO −  
SQDLAJ  
RXI +  
1
2
3
4
5
6
7
8
16  
CC  
Adjustable Squelch Delay  
15 DATEN  
Direct TTL-Level Squelch Output  
14  
13  
12  
11  
10  
9
DRI  
Squelch Circuit Allows for External Noise  
DLEN  
RXO  
Filtering  
SQO  
RXI −  
Two Driver-Enable Options  
SQDLI  
SQRXO  
SQTHAJ  
GND  
On-Chip Start-of-Idle Detection and Disable  
Driver Provides 2-V Minimum into a 50-Ω  
Differential Load Allowing for Use With  
Doubly-Terminated Lines and Multipoint  
Architectures  
On-Chip Driver Slew-Rate Control for Very  
Closely Matched Output Rise and Fall  
Times  
Function Tables  
§
DRIVER  
RECEIVER  
INPUTS  
DATEN DLEN DRO + DRO −  
INPUTS  
OUTPUTS  
OUTPUTS  
CONDITION  
RXI +  
RXI −  
RXO  
SQO  
DRI  
No active signal  
X
L
H
X
H
L
H
L
H
H
L
L
L
L
L
H
H
H
X
X
H
L
L
H
Z
H
L
Z
H
X
H
L
Active signal  
H
L
L
H
L
This condition is valid during the time period set by DRDLAJ following a rising transition on DRI. Following this, when a  
subsequent positive transition does not occur on DRI, the outputs go to the high-impedance state.  
This condition is valid when it occurs within the enable time set by DRDLAJ after a rising transition on DRI. Otherwise, the  
outputs are in the high-impedance state.  
§
Pins 9 and 10 are tied together.  
An active signal is one that has an amplitude greater than the threshold level set by SQTHAJ.  
ꢒꢤ  
Copyright 1990, Texas Instruments Incorporated  
ꢠ ꢤ ꢡ ꢠꢙ ꢚꢮ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢩ  
2−1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  

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