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SN75061N PDF预览

SN75061N

更新时间: 2024-02-28 17:12:06
品牌 Logo 应用领域
德州仪器 - TI 驱动器网络接口电信集成电路电信电路光电二极管以太网:16GBASE-T
页数 文件大小 规格书
13页 197K
描述
DRIVER/RECEIVER PAIR WITH SQUELCH

SN75061N 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete零件包装代码:DIP
包装说明:PLASTIC, DIP-16针数:16
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.9Is Samacsys:N
数据速率:1000 MbpsJESD-30 代码:R-PDIP-T16
长度:19.305 mm功能数量:1
端子数量:16收发器数量:1
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:Network Interfaces最大压摆率:0.07 mA
标称供电电压:5 V表面贴装:NO
技术:BIPOLAR电信集成电路类型:ETHERNET TRANSCEIVER
温度等级:COMMERCIAL端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

SN75061N 数据手册

 浏览型号SN75061N的Datasheet PDF文件第2页浏览型号SN75061N的Datasheet PDF文件第3页浏览型号SN75061N的Datasheet PDF文件第4页浏览型号SN75061N的Datasheet PDF文件第5页浏览型号SN75061N的Datasheet PDF文件第6页浏览型号SN75061N的Datasheet PDF文件第7页 
ꢀ ꢁꢂ ꢃꢄ ꢅꢆ  
ꢇꢈꢉ ꢊꢋ ꢈꢌꢈꢋ ꢍꢋꢉ ꢊꢋꢈ ꢎꢏꢐꢉ ꢈꢎꢑ ꢉꢒ ꢓꢎ ꢀ ꢔꢕ ꢋ ꢖꢍ ꢓ  
SLLS026C − JANUARY 1987 − REVISED JULY 1990  
N PACKAGE  
(TOP VIEW)  
IEEE 802.3 1BASE5 Driver and Receiver  
On-Chip Receiver Squelch With Adjustable  
Threshold  
V
DRDLAJ  
DRO +  
DRO −  
SQDLAJ  
RXI +  
1
2
3
4
5
6
7
8
16  
CC  
Adjustable Squelch Delay  
15 DATEN  
Direct TTL-Level Squelch Output  
14  
13  
12  
11  
10  
9
DRI  
Squelch Circuit Allows for External Noise  
DLEN  
RXO  
Filtering  
SQO  
RXI −  
Two Driver-Enable Options  
SQDLI  
SQRXO  
SQTHAJ  
GND  
On-Chip Start-of-Idle Detection and Disable  
Driver Provides 2-V Minimum into a 50-Ω  
Differential Load Allowing for Use With  
Doubly-Terminated Lines and Multipoint  
Architectures  
On-Chip Driver Slew-Rate Control for Very  
Closely Matched Output Rise and Fall  
Times  
Function Tables  
§
DRIVER  
RECEIVER  
INPUTS  
DATEN DLEN DRO + DRO −  
INPUTS  
OUTPUTS  
OUTPUTS  
CONDITION  
RXI +  
RXI −  
RXO  
SQO  
DRI  
No active signal  
X
L
H
X
H
L
H
L
H
H
L
L
L
L
L
H
H
H
X
X
H
L
L
H
Z
H
L
Z
H
X
H
L
Active signal  
H
L
L
H
L
This condition is valid during the time period set by DRDLAJ following a rising transition on DRI. Following this, when a  
subsequent positive transition does not occur on DRI, the outputs go to the high-impedance state.  
This condition is valid when it occurs within the enable time set by DRDLAJ after a rising transition on DRI. Otherwise, the  
outputs are in the high-impedance state.  
§
Pins 9 and 10 are tied together.  
An active signal is one that has an amplitude greater than the threshold level set by SQTHAJ.  
ꢒꢤ  
Copyright 1990, Texas Instruments Incorporated  
ꢠ ꢤ ꢡ ꢠꢙ ꢚꢮ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢩ  
2−1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  

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