Datasheet > 存储 > FIFO> SN74V225-10PAG

SN74V225-10PAG

更新时间： 2024-01-02 14:19:57

品牌	Logo	应用领域
德州仪器 - TI		存储内存集成电路先进先出芯片时钟
页数	文件大小	规格书
43页	591K
描述
512 X 18, 1024 X 18, 2048 X 18, 4096 X 18 DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES

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技术参数
数据手册
替代型号

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SN74V225-10PAG 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	GREEN, PLASTIC, TQFP-64	针数：	64
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.32.00.71	Factory Lead Time：	1 week
风险等级：	5.75	Is Samacsys：	N
最长访问时间：	6.5 ns	最大时钟频率 (fCLK)：	100 MHz
周期时间：	10 ns	JESD-30 代码：	S-PQFP-G64
JESD-609代码：	e4	长度：	10 mm
内存密度：	18432 bit	内存集成电路类型：	OTHER FIFO
内存宽度：	18	湿度敏感等级：	3
功能数量：	1	端子数量：	64
字数：	1024 words	字数代码：	1000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	1KX18
可输出：	YES	封装主体材料：	PLASTIC/EPOXY
封装代码：	TFQFP	封装等效代码：	TQFP64,.47SQ
封装形状：	SQUARE	封装形式：	FLATPACK, THIN PROFILE, FINE PITCH
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	260
电源：	3.3 V	认证状态：	Not Qualified
座面最大高度：	1.2 mm	子类别：	FIFOs
最大压摆率：	0.035 mA	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	10 mm	Base Number Matches：	1

SN74V225-10PAG 数据手册

SN74V215, SN74V225, SN74V235, SN74V245

512 × 18, 1024 × 18, 2048 × 18, 4096 × 18

DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES

SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002

512 × 18-Bit Organization Array (SN74V215)

Asynchronous or Coincident Read and

Write Clocks

1024 × 18-Bit Organization Array

(SN74V225)

Asynchronous or Synchronous

Programmable Almost-Empty and

Almost-Full Flags With Default Settings

2048 × 18-Bit Organization Array

(SN74V235)

Half-Full Flag Capability

4096 × 18-Bit Organization Array

(SN74V245)

Output Enable Puts Output Data Bus in

High-Impedance State

7.5-ns Read/Write Cycle Time

High-Performance Submicron CMOS

Technology

3.3-V V , 5-V Input Tolerant

First-Word or Standard Fall-Through

Timing

Packaged in 64-Pin Thin Quad Flat Package

DSP and Microprocessor Interface Control

Logic

Single or Double Register-Buffered Empty

and Full Flags

Provide a DSP Glueless Interface to Texas

Instruments TMS320 DSPs

Easily Expandable in Depth and Width

description

TheSN74V215, SN74V225, SN74V235, andSN74V245areveryhigh-speed, low-powerCMOSclockedfirst-in

first-out (FIFO) memories. They support clock frequencies up to 133 MHz and have read-access times as fast

as 5 ns. These DSP-Sync FIFO memories feature read and write controls for use in applications such as

DSP-to-processor communication, DSP-to-analog front end (AFE) buffering, network, video, and data

communications.

These are synchronous FIFOs, which means each port employs a synchronous interface. All data transfers

through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable signals.

The continuous clocks for each port are independent of one another and can be asynchronous or coincident.

The enables for each port are arranged to provide a simple interface between DSPs, microprocessors, and/or

buses controlled by a synchronous interface. An output-enable (OE) input controls the 3-state output.

The synchronous FIFOs have two fixed flags, empty flag/output ready (EF/OR) and full flag/input ready (FF/IR),

and two programmable flags, almost-empty (PAE) and almost-full (PAF). The offset loading of the

programmable flags is controlled by a simple state machine, and is initiated by asserting the load pin (LD). A

half-full flag (HF) is available when the FIFO is used in a single-device configuration.

Two timing modes of operation are possible with these devices: first-word fall-through (FWFT) mode and

standard mode.

In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three

transitions of the RCLK signal. A read enable (REN) does not have to be asserted for accessing the first word.

In standard mode, the first word written to an empty FIFO does not appear on the data output lines unless a

specific read operation is performed. A read operation, which consists of activating REN and enabling a rising

RCLK edge, shifts the word from internal memory to the data output lines.

These devices are depth expandable, using a daisy-chain technique or FWFT mode. The XI and XO pins are

used to expand the FIFOs. In depth-expansion configuration, first load (FL) is grounded on the first device and

set to high for all other devices in the daisy chain.

The SN74V215, SN74V225, SN74V235, and SN74V245 are characterized for operation from 0°C to 70°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

DSP-SYNC and TMS320 are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...43

中文翻译

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SN74V225-10PAG 替代型号

型号	品牌	替代类型	描述	数据表
72V225L10TFG	IDT	类似代替	3.3 VOLT CMOS SyncFIFO
72225LB25PFI	IDT	功能相似	TQFP-64, Tray
CY7C4225-10AXI	CYPRESS	功能相似	256/512/1K/4K x 18 Synchronous FIFOs

与SN74V225-10PAG相关器件

型号	品牌	获取价格	描述	数据表
SN74V225-15PAG	TI	获取价格	512 X 18, 1024 X 18, 2048 X 18, 4096 X 18 DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SN74V225-20PAG	TI	获取价格	512 X 18, 1024 X 18, 2048 X 18, 4096 X 18 DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SN74V225-7PAG	TI	获取价格	512 X 18, 1024 X 18, 2048 X 18, 4096 X 18 DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SN74V235	TI	获取价格	512 X 18, 1024 X 18, 2048 X 18, 4096 X 18 DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SN74V235-10PAG	TI	获取价格	512 X 18, 1024 X 18, 2048 X 18, 4096 X 18 DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SN74V235-15PAG	TI	获取价格	512 X 18, 1024 X 18, 2048 X 18, 4096 X 18 DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SN74V235-20PAG	TI	获取价格	512 X 18, 1024 X 18, 2048 X 18, 4096 X 18 DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SN74V235-7PAG	TI	获取价格	512 X 18, 1024 X 18, 2048 X 18, 4096 X 18 DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SN74V245	TI	获取价格	512 X 18, 1024 X 18, 2048 X 18, 4096 X 18 DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SN74V245-10PAG	TI	获取价格	512 X 18, 1024 X 18, 2048 X 18, 4096 X 18 DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES

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