5秒后页面跳转
捷配首页

Datasheet > 存储 > FIFO> SN74V263-6PZA
SN74V263-6PZA PDF预览

SN74V263-6PZA

更新时间： 2024-11-21 04:31:15
品牌 Logo 应用领域
德州仪器 - TI 存储内存集成电路先进先出芯片时钟
页数 文件大小 规格书
52页 793K
描述
8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES

阅读下载

中文翻译

获取价格

SN74V263-6PZA 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFP
包装说明：LQFP, QFP80,.64SQ针数：80
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.77
最长访问时间：4.5 ns其他特性：CAN ALSO BE CONFIGURED AS 16384 X 9
备用内存宽度：9最大时钟频率 (fCLK)：166 MHz
周期时间：6 nsJESD-30 代码：S-PQFP-G80
JESD-609代码：e4长度：14 mm
内存密度：147456 bit内存集成电路类型：OTHER FIFO
内存宽度：18湿度敏感等级：4
功能数量：1端子数量：80
字数：8192 words字数代码：8000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：8KX18
输出特性：3-STATE可输出：YES
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装等效代码：QFP80,.64SQ封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：260电源：3.3 V
认证状态：Not Qualified座面最大高度：1.6 mm
最大待机电流：0.015 A子类别：FIFOs
最大压摆率：0.035 mA最大供电电压 (Vsup)：3.45 V
最小供电电压 (Vsup)：3.15 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mmBase Number Matches：1

SN74V263-6PZA 数据手册

 浏览型号SN74V263-6PZA的Datasheet PDF文件第2页浏览型号SN74V263-6PZA的Datasheet PDF文件第3页浏览型号SN74V263-6PZA的Datasheet PDF文件第4页浏览型号SN74V263-6PZA的Datasheet PDF文件第5页浏览型号SN74V263-6PZA的Datasheet PDF文件第6页浏览型号SN74V263-6PZA的Datasheet PDF文件第7页 
SN74V263, SN74V273, SN74V283, SN74V293  
8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18  
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES  
SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003  
Choice of Memory Organizations  
– SN74V263 – 8192 × 18/16384 × 9  
– SN74V273 – 16384 × 18/32768 × 9  
– SN74V283 – 32768 × 18/65536 × 9  
– SN74V293 – 65536 × 18/131072 × 9  
Programmable Almost-Empty and  
Almost-Full Flags; Each Flag Can Default to  
One of Eight Preselected Offsets  
Selectable Synchronous/Asynchronous  
Timing Modes for Almost-Empty and  
Almost-Full Flags  
166-MHz Operation  
6-ns Read/Write Cycle Time  
Program Programmable Flags by Either  
Serial or Parallel Means  
User-Selectable Input and Output Port Bus  
Sizing  
– ×9 in to ×9 out  
Select Standard Timing (Using EF and FF  
Flags) or First-Word Fall-Through (FWFT)  
Timing (Using OR and IR Flags)  
– ×9 in to ×18 out  
– ×18 in to ×9 out  
– ×18 in to ×18 out  
Output Enable Puts Data Outputs in  
High-Impedance State  
Big-Endian/Little-Endian User-Selectable  
Byte Representation  
Easily Expandable in Depth and Width  
Independent Read and Write Clocks Permit  
Reading and Writing Simultaneously  
5-V-Tolerant Inputs  
Fixed, Low First-Word Latency  
Zero-Latency Retransmit  
Master Reset Clears Entire FIFO  
High-Performance Submicron CMOS  
Technology  
Glueless Interface With ’C6x DSPs  
Partial Reset Clears Data, but Retains  
Programmable Settings  
Available in 80-Pin Thin Quad Flat Pack  
(TQFP) and 100-Pin Ball Grid Array (BGA)  
Packages  
Empty, Full, and Half-Full Flags Signal FIFO  
Status  
description  
The SN74V263, SN74V273, SN74V283, and SN74V293 are exceptionally deep, high-speed, CMOS first-in  
first-out (FIFO) memories with clocked read and write controls and a flexible bus-matching ×9/×18 data flow.  
There is flexible ×9/×18 bus matching on both read and write ports.  
The period required by the retransmit operation is fixed and short.  
The first-word data-latency period, from the time the first word is written to an empty FIFO to the time it can be  
read, is fixed and short.  
These FIFOs are particularly appropriate for network, video, telecommunications, data communications, and  
other applications that need to buffer large amounts of data and match buses of unequal sizes.  
Each FIFO has a data input port (Dn) and a data output port (Qn), both of which can assume either an 18-bit  
or 9-bit width, as determined by the state of external control pins’ input width (IW) and output width (OW) during  
the master-reset cycle.  
The input port is controlled by write-clock (WCLK) and write-enable (WEN) inputs. Data is written into the FIFO  
on every rising edge of WCLK when WEN is asserted. The output port is controlled by read-clock (RCLK) and  
read-enable (REN) inputs. Data is read from the FIFO on every rising edge of RCLK when REN is asserted.  
An output-enable (OE) input is provided for 3-state control of the outputs.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...52

中文翻译

下载PDF

SN74V263-6PZA 替代型号

型号 品牌 替代类型 描述 数据表
SN74V263PZAEP TI

类似代替

 Enhanced Product 8192 X 18 Synchronous Fifo Memory 80-LQFP -55 to 125
SN74V263-7PZA TI

类似代替

 8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18

与SN74V263-6PZA相关器件

型号 品牌 获取价格 描述 数据表
SN74V263-7.5GGM TI

获取价格

 		8KX18 OTHER FIFO, 5ns, PBGA100, BGA-100
SN74V263-7GGM TI

获取价格

 		8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18
SN74V263-7PZA TI

获取价格

 		8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18
SN74V263-EP TI

获取价格

 		3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SN74V263PZAEP TI

获取价格

 		Enhanced Product 8192 X 18 Synchronous Fifo Memory 80-LQFP -55 to 125
SN74V273 TI

获取价格

 		8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18
SN74V273-10GGM TI

获取价格

 		8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18
SN74V273-10PZA TI

获取价格

 		8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18
SN74V273-15GGM TI

获取价格

 		8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18
SN74V273-15PZA TI

获取价格

 		8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18

与SN74V263-6PZA相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证