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SN74V283-15PZAG4 PDF预览

SN74V283-15PZAG4

更新时间： 2024-11-21 15:52:23
品牌 Logo 应用领域
德州仪器 - TI 时钟先进先出芯片内存集成电路
页数 文件大小 规格书
52页 829K
描述
32KX18 OTHER FIFO, 10ns, PQFP80, GREEN, PLASTIC, LQFP-80

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SN74V283-15PZAG4 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：QFP
包装说明：LQFP, QFP80,.64SQ针数：80
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.71风险等级：5.51
Is Samacsys：N最长访问时间：10 ns
其他特性：CAN ALSO BE CONFIGURED AS 65536 X 9备用内存宽度：9
最大时钟频率 (fCLK)：66.7 MHz周期时间：15 ns
JESD-30 代码：S-PQFP-G80JESD-609代码：e4
长度：14 mm内存密度：589824 bit
内存集成电路类型：OTHER FIFO内存宽度：18
湿度敏感等级：4功能数量：1
端子数量：80字数：32768 words
字数代码：32000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：32KX18可输出：YES
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装等效代码：QFP80,.64SQ封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：260电源：3.3 V
认证状态：Not Qualified座面最大高度：1.6 mm
最大待机电流：0.015 A子类别：FIFOs
最大压摆率：0.035 mA最大供电电压 (Vsup)：3.45 V
最小供电电压 (Vsup)：3.15 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mmBase Number Matches：1

SN74V283-15PZAG4 数据手册

 浏览型号SN74V283-15PZAG4的Datasheet PDF文件第2页浏览型号SN74V283-15PZAG4的Datasheet PDF文件第3页浏览型号SN74V283-15PZAG4的Datasheet PDF文件第4页浏览型号SN74V283-15PZAG4的Datasheet PDF文件第5页浏览型号SN74V283-15PZAG4的Datasheet PDF文件第6页浏览型号SN74V283-15PZAG4的Datasheet PDF文件第7页 
SN74V263, SN74V273, SN74V283, SN74V293  
8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18  
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES  
SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003  
Choice of Memory Organizations  
– SN74V263 – 8192 × 18/16384 × 9  
– SN74V273 – 16384 × 18/32768 × 9  
– SN74V283 – 32768 × 18/65536 × 9  
– SN74V293 – 65536 × 18/131072 × 9  
Programmable Almost-Empty and  
Almost-Full Flags; Each Flag Can Default to  
One of Eight Preselected Offsets  
Selectable Synchronous/Asynchronous  
Timing Modes for Almost-Empty and  
Almost-Full Flags  
166-MHz Operation  
6-ns Read/Write Cycle Time  
Program Programmable Flags by Either  
Serial or Parallel Means  
User-Selectable Input and Output Port Bus  
Sizing  
– ×9 in to ×9 out  
Select Standard Timing (Using EF and FF  
Flags) or First-Word Fall-Through (FWFT)  
Timing (Using OR and IR Flags)  
– ×9 in to ×18 out  
– ×18 in to ×9 out  
– ×18 in to ×18 out  
Output Enable Puts Data Outputs in  
High-Impedance State  
Big-Endian/Little-Endian User-Selectable  
Byte Representation  
Easily Expandable in Depth and Width  
Independent Read and Write Clocks Permit  
Reading and Writing Simultaneously  
5-V-Tolerant Inputs  
Fixed, Low First-Word Latency  
Zero-Latency Retransmit  
Master Reset Clears Entire FIFO  
High-Performance Submicron CMOS  
Technology  
Glueless Interface With ’C6x DSPs  
Partial Reset Clears Data, but Retains  
Programmable Settings  
Available in 80-Pin Thin Quad Flat Pack  
(TQFP) and 100-Pin Ball Grid Array (BGA)  
Packages  
Empty, Full, and Half-Full Flags Signal FIFO  
Status  
description  
The SN74V263, SN74V273, SN74V283, and SN74V293 are exceptionally deep, high-speed, CMOS first-in  
first-out (FIFO) memories with clocked read and write controls and a flexible bus-matching ×9/×18 data flow.  
There is flexible ×9/×18 bus matching on both read and write ports.  
The period required by the retransmit operation is fixed and short.  
The first-word data-latency period, from the time the first word is written to an empty FIFO to the time it can be  
read, is fixed and short.  
These FIFOs are particularly appropriate for network, video, telecommunications, data communications, and  
other applications that need to buffer large amounts of data and match buses of unequal sizes.  
Each FIFO has a data input port (Dn) and a data output port (Qn), both of which can assume either an 18-bit  
or 9-bit width, as determined by the state of external control pins’ input width (IW) and output width (OW) during  
the master-reset cycle.  
The input port is controlled by write-clock (WCLK) and write-enable (WEN) inputs. Data is written into the FIFO  
on every rising edge of WCLK when WEN is asserted. The output port is controlled by read-clock (RCLK) and  
read-enable (REN) inputs. Data is read from the FIFO on every rising edge of RCLK when REN is asserted.  
An output-enable (OE) input is provided for 3-state control of the outputs.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...52

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 		8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18
SN74V283-6PZA TI

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 		8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18
SN74V283-7.5GGM TI

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SN74V283-7GGM TI

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 		8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18
SN74V283-7PZA TI

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 		8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18
SN74V283PZAEP TI

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 		Enhanced Product 32768 X 18 Synchronous Fifo Memory 80-LQFP -55 to 125
SN74V293 TI

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 		8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18
SN74V293-10GGM TI

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 		8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18
SN74V293-10PZA TI

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 		8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18
SN74V293-15GGM TI

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 		8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18

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