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SN74V293 PDF预览

SN74V293

更新时间: 2024-01-28 16:55:42
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
48页 709K
描述
8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES

SN74V293 数据手册

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SN74V263, SN74V273, SN74V283, SN74V293  
8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18  
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES  
SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003  
Choice of Memory Organizations  
– SN74V263 – 8192 × 18/16384 × 9  
– SN74V273 – 16384 × 18/32768 × 9  
– SN74V283 – 32768 × 18/65536 × 9  
– SN74V293 – 65536 × 18/131072 × 9  
Programmable Almost-Empty and  
Almost-Full Flags; Each Flag Can Default to  
One of Eight Preselected Offsets  
Selectable Synchronous/Asynchronous  
Timing Modes for Almost-Empty and  
Almost-Full Flags  
166-MHz Operation  
6-ns Read/Write Cycle Time  
Program Programmable Flags by Either  
Serial or Parallel Means  
User-Selectable Input and Output Port Bus  
Sizing  
×9 in to ×9 out  
Select Standard Timing (Using EF and FF  
Flags) or First-Word Fall-Through (FWFT)  
Timing (Using OR and IR Flags)  
×9 in to ×18 out  
×18 in to ×9 out  
×18 in to ×18 out  
Output Enable Puts Data Outputs in  
High-Impedance State  
Big-Endian/Little-Endian User-Selectable  
Byte Representation  
Easily Expandable in Depth and Width  
Independent Read and Write Clocks Permit  
Reading and Writing Simultaneously  
5-V-Tolerant Inputs  
Fixed, Low First-Word Latency  
Zero-Latency Retransmit  
Master Reset Clears Entire FIFO  
High-Performance Submicron CMOS  
Technology  
Glueless Interface With ’C6x DSPs  
Partial Reset Clears Data, but Retains  
Programmable Settings  
Available in 80-Pin Thin Quad Flat Pack  
(TQFP) and 100-Pin Ball Grid Array (BGA)  
Packages  
Empty, Full, and Half-Full Flags Signal FIFO  
Status  
description  
The SN74V263, SN74V273, SN74V283, and SN74V293 are exceptionally deep, high-speed, CMOS first-in  
first-out (FIFO) memories with clocked read and write controls and a flexible bus-matching ×9/×18 data flow.  
There is flexible ×9/×18 bus matching on both read and write ports.  
The period required by the retransmit operation is fixed and short.  
The first-word data-latency period, from the time the first word is written to an empty FIFO to the time it can be  
read, is fixed and short.  
These FIFOs are particularly appropriate for network, video, telecommunications, data communications, and  
other applications that need to buffer large amounts of data and match buses of unequal sizes.  
Each FIFO has a data input port (Dn) and a data output port (Qn), both of which can assume either an 18-bit  
or 9-bit width, as determined by the state of external control pins’ input width (IW) and output width (OW) during  
the master-reset cycle.  
The input port is controlled by write-clock (WCLK) and write-enable (WEN) inputs. Data is written into the FIFO  
on every rising edge of WCLK when WEN is asserted. The output port is controlled by read-clock (RCLK) and  
read-enable (REN) inputs. Data is read from the FIFO on every rising edge of RCLK when REN is asserted.  
An output-enable (OE) input is provided for 3-state control of the outputs.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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