SN74V3640-15PEU

更新时间： 2024-11-20 22:37:03

品牌	Logo	应用领域
德州仪器 - TI		/
页数	文件大小	规格书
50页	725K
描述
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES

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SN74V3640-15PEU 数据手册

SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690

1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36

3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES

SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003

Choice of Memory Organizations

Empty, Full, and Half-Full Flags Signal FIFO

Status

– SN74V3640 – 1024 × 36 Bit

– SN74V3650 – 2048 × 36 Bit

– SN74V3660 – 4096 × 36 Bit

– SN74V3670 – 8192 × 36 Bit

– SN74V3680 – 16384 × 36 Bit

– SN74V3690 – 32768 × 36 Bit

Programmable Almost-Empty and

Almost-Full Flags; Each Flag Can Default to

One of Eight Preselected Offsets

Selectable Synchronous/Asynchronous

Timing Modes for Almost-Empty and

Almost-Full Flags

166-MHz Operation (6-ns Read/Write Cycle

Time)

Program Programmable Flags by Either

Serial or Parallel Means

User-Selectable Input- and Output-Port Bus

Sizing

– ×36 in to ×36 out

– ×36 in to ×18 out

– ×36 in to ×9 out

Select Standard Timing (Using EF and FF

Flags) or First-Word Fall-Through (FWFT)

Timing (Using OR and IR Flags)

Output Enable Puts Data Outputs in

High-Impedance State

– ×18 in to ×36 out

– ×9 in to ×36 out

Easily Expandable in Depth and Width

Big-Endian/Little-Endian User-Selectable

Byte Representation

Independent Read and Write Clocks Permit

Reading and Writing Simultaneously

5-V-Tolerant Inputs

High-Performance Submicron CMOS

Technology

Fixed, Low, First-Word Latency

Zero-Latency Retransmit

Master Reset Clears Entire FIFO

Available in 128-Pin Thin Quad Flat Pack

(TQFP)

Partial Reset Clears Data, But Retains

Programmable Settings

description

The SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, and SN74V3690 are exceptionally

deep, high-speed CMOS, first-in first-out (FIFO) memories, with clocked read and write controls and a flexible

bus-matching ×36/×18/×9 data flow. These FIFOs offer several key user benefits:

Flexible ×36/×18/×9 bus matching on both read and write ports

The period required by the retransmit operation is fixed and short.

The first-word data-latency period, from the time the first word is written to an empty FIFO to the time it can

be read, is fixed and short.

High-density offerings up to 1 Mbit

Bus-matching synchronous FIFOs are particularly appropriate for network, video, signal processing,

telecommunications, data communications, and other applications that need to buffer large amounts of data

and match buses of unequal sizes.

Each FIFO has a data input port (Dn) and a data output port (Qn), both of which can assume 36-bit, 18-bit, or

9-bit width, as determined by the state of external control pins’ input width (IW), output width (OW), and bus

matching (BM) during the master-reset cycle.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...50

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与SN74V3640-15PEU相关器件

型号	品牌	获取价格	描述	数据表
SN74V3640-6PEU	TI	获取价格	3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SN74V3640-7.5PEU	TI	获取价格	1KX36 OTHER FIFO, 5ns, PQFP128, TQFP-128
SN74V3640-7PEU	TI	获取价格	3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SN74V3650	TI	获取价格	3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SN74V3650-10PEU	TI	获取价格	3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SN74V3650-15PEU	TI	获取价格	3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SN74V3650-6PEU	TI	获取价格	3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SN74V3650-7PEU	TI	获取价格	3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SN74V3660	TI	获取价格	3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SN74V3660-10PEU	TI	获取价格	3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES

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