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SN74V263-10PZA PDF预览

SN74V263-10PZA

更新时间： 2024-02-15 20:02:43
品牌 Logo 应用领域
德州仪器 - TI 存储内存集成电路先进先出芯片时钟
页数 文件大小 规格书
52页 793K
描述
8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES

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SN74V263-10PZA 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：QFP
包装说明：LQFP, QFP80,.64SQ针数：80
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.32.00.71风险等级：5.48
最长访问时间：6.5 ns其他特性：CAN ALSO BE CONFIGURED AS 16384 X 9
备用内存宽度：9最大时钟频率 (fCLK)：100 MHz
周期时间：10 nsJESD-30 代码：S-PQFP-G80
JESD-609代码：e4长度：14 mm
内存密度：147456 bit内存集成电路类型：OTHER FIFO
内存宽度：18湿度敏感等级：4
功能数量：1端子数量：80
字数：8192 words字数代码：8000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：8KX18
可输出：YES封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装等效代码：QFP80,.64SQ
封装形状：SQUARE封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
电源：3.3 V认证状态：Not Qualified
座面最大高度：1.6 mm最大待机电流：0.015 A
子类别：FIFOs最大压摆率：0.035 mA
最大供电电压 (Vsup)：3.45 V最小供电电压 (Vsup)：3.15 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：14 mm
Base Number Matches：1

SN74V263-10PZA 数据手册

 浏览型号SN74V263-10PZA的Datasheet PDF文件第2页浏览型号SN74V263-10PZA的Datasheet PDF文件第3页浏览型号SN74V263-10PZA的Datasheet PDF文件第4页浏览型号SN74V263-10PZA的Datasheet PDF文件第5页浏览型号SN74V263-10PZA的Datasheet PDF文件第6页浏览型号SN74V263-10PZA的Datasheet PDF文件第7页 
SN74V263, SN74V273, SN74V283, SN74V293  
8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18  
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES  
SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003  
Choice of Memory Organizations  
– SN74V263 – 8192 × 18/16384 × 9  
– SN74V273 – 16384 × 18/32768 × 9  
– SN74V283 – 32768 × 18/65536 × 9  
– SN74V293 – 65536 × 18/131072 × 9  
Programmable Almost-Empty and  
Almost-Full Flags; Each Flag Can Default to  
One of Eight Preselected Offsets  
Selectable Synchronous/Asynchronous  
Timing Modes for Almost-Empty and  
Almost-Full Flags  
166-MHz Operation  
6-ns Read/Write Cycle Time  
Program Programmable Flags by Either  
Serial or Parallel Means  
User-Selectable Input and Output Port Bus  
Sizing  
– ×9 in to ×9 out  
Select Standard Timing (Using EF and FF  
Flags) or First-Word Fall-Through (FWFT)  
Timing (Using OR and IR Flags)  
– ×9 in to ×18 out  
– ×18 in to ×9 out  
– ×18 in to ×18 out  
Output Enable Puts Data Outputs in  
High-Impedance State  
Big-Endian/Little-Endian User-Selectable  
Byte Representation  
Easily Expandable in Depth and Width  
Independent Read and Write Clocks Permit  
Reading and Writing Simultaneously  
5-V-Tolerant Inputs  
Fixed, Low First-Word Latency  
Zero-Latency Retransmit  
Master Reset Clears Entire FIFO  
High-Performance Submicron CMOS  
Technology  
Glueless Interface With ’C6x DSPs  
Partial Reset Clears Data, but Retains  
Programmable Settings  
Available in 80-Pin Thin Quad Flat Pack  
(TQFP) and 100-Pin Ball Grid Array (BGA)  
Packages  
Empty, Full, and Half-Full Flags Signal FIFO  
Status  
description  
The SN74V263, SN74V273, SN74V283, and SN74V293 are exceptionally deep, high-speed, CMOS first-in  
first-out (FIFO) memories with clocked read and write controls and a flexible bus-matching ×9/×18 data flow.  
There is flexible ×9/×18 bus matching on both read and write ports.  
The period required by the retransmit operation is fixed and short.  
The first-word data-latency period, from the time the first word is written to an empty FIFO to the time it can be  
read, is fixed and short.  
These FIFOs are particularly appropriate for network, video, telecommunications, data communications, and  
other applications that need to buffer large amounts of data and match buses of unequal sizes.  
Each FIFO has a data input port (Dn) and a data output port (Qn), both of which can assume either an 18-bit  
or 9-bit width, as determined by the state of external control pins’ input width (IW) and output width (OW) during  
the master-reset cycle.  
The input port is controlled by write-clock (WCLK) and write-enable (WEN) inputs. Data is written into the FIFO  
on every rising edge of WCLK when WEN is asserted. The output port is controlled by read-clock (RCLK) and  
read-enable (REN) inputs. Data is read from the FIFO on every rising edge of RCLK when REN is asserted.  
An output-enable (OE) input is provided for 3-state control of the outputs.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...52

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SN74V263-15GGM TI

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 		8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18
SN74V263-15PZA TI

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 		8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18
SN74V263-6GGM TI

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 		8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18
SN74V263-6PZA TI

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 		8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18
SN74V263-7.5GGM TI

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 		8KX18 OTHER FIFO, 5ns, PBGA100, BGA-100
SN74V263-7GGM TI

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 		8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18
SN74V263-7PZA TI

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 		8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18
SN74V263-EP TI

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 		3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SN74V263PZAEP TI

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 		Enhanced Product 8192 X 18 Synchronous Fifo Memory 80-LQFP -55 to 125
SN74V273 TI

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 		8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18

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