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SN74LVT652PWLE PDF预览

SN74LVT652PWLE

更新时间： 2024-09-16 18:43:03
品牌 Logo 应用领域
德州仪器 - TI 输入元件信息通信管理光电二极管逻辑集成电路触发器
页数 文件大小 规格书
13页 270K
描述
3.3-V ABT Octal Bus Transceivers And Registers With 3-State Outputs 24-TSSOP -40 to 85

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中文翻译

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SN74LVT652PWLE 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP, TSSOP24,.25针数：24
Reach Compliance Code：not_compliantHTS代码：8542.39.00.01
风险等级：5.4其他特性：SELECT INPUT FOR MULTIPLEXED TRANSMISSION OF REGISTERED/REAL TIME DATA
控制类型：INDEPENDENT CONTROL计数方向：BIDIRECTIONAL
系列：LVTJESD-30 代码：R-PDSO-G24
长度：7.8 mm负载电容（CL）：50 pF
逻辑集成电路类型：REGISTERED BUS TRANSCEIVER最大I（ol）：0.064 A
位数：8功能数量：1
端口数量：2端子数量：24
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP24,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法：TAPE AND REEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：3.3 V
最大电源电流（ICC）：12 mAProp。Delay @ Nom-Sup：4.7 ns
传播延迟（tpd）：6.4 ns认证状态：Not Qualified
座面最大高度：1.2 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.7 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：BICMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
翻译：N/A触发器类型：POSITIVE EDGE
宽度：4.4 mmBase Number Matches：1

SN74LVT652PWLE 数据手册

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SCBS141E − MAY 1992 − REVISED JULY 1995  
SN54LVT652 . . . JT PACKAGE  
SN74LVT652 . . . DB, DW, OR PW PACKAGE  
(TOP VIEW)  
D State-of-the-Art Advanced BiCMOS  
Technology (ABT) Design for 3.3-V  
Operation and Low-Static Power  
Dissipation  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
CLKAB  
SAB  
OEAB  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
GND  
V
CC  
D Support Mixed-Mode Signal Operation (5-V  
2
CLKBA  
SBA  
OEBA  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
Input and Output Voltages With 3.3-V V  
)
CC  
3
D Support Unregulated Battery Operation  
4
Down to 2.7 V  
5
6
D Typical V  
(Output Ground Bounce)  
OLP  
7
< 0.8 V at V  
= 3.3 V, T = 25°C  
CC  
A
8
D ESD Protection Exceeds 2000 V Per  
MIL-STD-883C, Method 3015; Exceeds  
200 V Using Machine Model  
9
10  
11  
12  
(C = 200 pF, R = 0)  
B8  
D Latch-Up Performance Exceeds 500 mA  
Per JEDEC Standard JESD-17  
SN54LVT652 . . . FK PACKAGE  
(TOP VIEW)  
D Bus-Hold Data Inputs Eliminate the Need  
for External Pullup Resistors  
D Support Live Insertion  
D Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
4
3
2 1 28 27 26  
25  
24  
23  
22  
21  
20  
19  
5
6
7
8
9
A1  
A2  
A3  
NC  
A4  
OEBA  
B1  
B2  
NC  
B3  
B4  
Packages, Ceramic Chip Carriers (FK), and  
Ceramic (JT) DIPs  
description  
These bus transceivers and registers are  
A5 10  
A6 11  
designed specifically for low-voltage (3.3-V) V  
B5  
CC  
12 13 14 15 16 17 18  
operation, but with the capability to provide a TTL  
interface to a 5-V system environment.  
The ’LVT652 consist of bus transceiver circuits,  
D-type flip-flops, and control circuitry arranged for  
multiplexed transmission of data directly from the  
data bus or from the internal storage registers.  
NC − No internal connection  
Output-enable (OEAB and OEBA) inputs are provided to control the transceiver functions. Select-control (SAB  
and SBA) inputs are provided to select whether real-time or stored data is transferred. The circuitry used for  
select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between  
real-time and stored data. A low input selects real-time data and a high input selects stored data. Figure 1  
illustrates the four fundamental bus-management functions that can be performed with the ′LVT652.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1995, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
1234567...13

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