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SN74LVT125_06

更新时间： 2024-02-10 06:44:49
品牌 Logo 应用领域
德州仪器 - TI 输出元件
页数 文件大小 规格书
12页 277K
描述
3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS

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中文翻译

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SN74LVT125_06 数据手册

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SCBS133F − MAY 1992 − REVISED OCTOBER 2003  
D, DB, NS, OR PW PACKAGE  
(TOP VIEW)  
D
Supports Mixed-Mode Signal Operation  
(5-V Input and Output Voltages With  
3.3-V V  
)
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
1OE  
1A  
1Y  
2OE  
2A  
2Y  
V
CC  
4OE  
D
D
D
D
D
D
Supports Unregulated Battery Operation  
Down to 2.7 V  
4A  
4Y  
3OE  
3A  
3Y  
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
= 3.3 V, T = 25°C  
A
I
Supports Partial-Power-Down Mode  
off  
8
Operation  
GND  
Bus-Hold Data Inputs Eliminate the Need  
for External Pullup Resistors  
Latch-Up Performance Exceeds 500 mA  
Per JEDEC Standard JESD-17  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
description/ordering information  
This bus buffer is designed specifically for low-voltage (3.3-V) V  
a TTL interface to a 5-V system environment.  
operation, but with the capability to provide  
CC  
The SN74LVT125 features independent line drivers with 3-state outputs. Each output is in the high-impedance  
state when the associated output-enable (OE) input is high.  
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors  
with the bus-hold circuitry is not recommended.  
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,  
off  
off  
preventing damaging current backflow through the device when it is powered down.  
To ensure the high-impedance state during power up or power down, OE should be tied to V  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
through a pullup  
CC  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
Tube  
SN74LVT125D  
SOIC − D  
LVT125  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SN74LVT125DR  
SN74LVT125NSR  
SN74LVT125DBR  
SN74LVT125PW  
SN74LVT125PWR  
SOP − NS  
LVT125  
LX125  
−40°C to 85°C  
SSOP − DB  
TSSOP − PW  
LX125  
Tape and reel  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
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Copyright 2003, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...12

中文翻译

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