5秒后页面跳转
捷配首页

Datasheet > SN74LVT125_06
SN74LVT125_06 PDF预览

SN74LVT125_06

更新时间： 2024-11-29 05:04:43
品牌 Logo 应用领域
德州仪器 - TI 输出元件
页数 文件大小 规格书
12页 277K
描述
3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS

阅读下载

中文翻译

获取价格

SN74LVT125_06 数据手册

 浏览型号SN74LVT125_06的Datasheet PDF文件第2页浏览型号SN74LVT125_06的Datasheet PDF文件第3页浏览型号SN74LVT125_06的Datasheet PDF文件第4页浏览型号SN74LVT125_06的Datasheet PDF文件第5页浏览型号SN74LVT125_06的Datasheet PDF文件第6页浏览型号SN74LVT125_06的Datasheet PDF文件第7页 
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇꢈ ꢉ  
ꢊ ꢋꢊ ꢌꢅ ꢍꢎꢆ ꢏ ꢐꢍꢑꢒ ꢐꢓꢄ ꢔ ꢎꢐꢀ ꢎ ꢐꢕ ꢕꢔ ꢒ  
ꢖ ꢗꢆ ꢘ ꢊ ꢌꢀꢆꢍꢆ ꢔ ꢙ ꢐꢆ ꢓ ꢐꢆꢀ  
SCBS133F − MAY 1992 − REVISED OCTOBER 2003  
D, DB, NS, OR PW PACKAGE  
(TOP VIEW)  
D
Supports Mixed-Mode Signal Operation  
(5-V Input and Output Voltages With  
3.3-V V  
)
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
1OE  
1A  
1Y  
2OE  
2A  
2Y  
V
CC  
4OE  
D
D
D
D
D
D
Supports Unregulated Battery Operation  
Down to 2.7 V  
4A  
4Y  
3OE  
3A  
3Y  
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
= 3.3 V, T = 25°C  
A
I
Supports Partial-Power-Down Mode  
off  
8
Operation  
GND  
Bus-Hold Data Inputs Eliminate the Need  
for External Pullup Resistors  
Latch-Up Performance Exceeds 500 mA  
Per JEDEC Standard JESD-17  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
description/ordering information  
This bus buffer is designed specifically for low-voltage (3.3-V) V  
a TTL interface to a 5-V system environment.  
operation, but with the capability to provide  
CC  
The SN74LVT125 features independent line drivers with 3-state outputs. Each output is in the high-impedance  
state when the associated output-enable (OE) input is high.  
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors  
with the bus-hold circuitry is not recommended.  
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,  
off  
off  
preventing damaging current backflow through the device when it is powered down.  
To ensure the high-impedance state during power up or power down, OE should be tied to V  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
through a pullup  
CC  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
Tube  
SN74LVT125D  
SOIC − D  
LVT125  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SN74LVT125DR  
SN74LVT125NSR  
SN74LVT125DBR  
SN74LVT125PW  
SN74LVT125PWR  
SOP − NS  
LVT125  
LX125  
−40°C to 85°C  
SSOP − DB  
TSSOP − PW  
LX125  
Tape and reel  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢓ
ꢓ
ꢒ
ꢙ
ꢪ
ꢑ
ꢥ
ꢐ
ꢚ
ꢣ
ꢆ
ꢤ
ꢗ
ꢞ
ꢙ
ꢜ
ꢁ
ꢝ
ꢑ
ꢍ
ꢆ
ꢍ
ꢛ
ꢜ
ꢦ
ꢝ
ꢞ
ꢤ
ꢟ
ꢠ
ꢡ
ꢡ
ꢢ
ꢢ
ꢛ
ꢛ
ꢞ
ꢞ
ꢜ
ꢜ
ꢛ
ꢣ
ꢣ
ꢧ
ꢤ
ꢥ
ꢟ
ꢟ
ꢦ
ꢦ
ꢜ
ꢢ
ꢡ
ꢠ
ꢣ
ꢣ
ꢞ
ꢝ
ꢧ
ꢆꢦ  
ꢥ
ꢨ
ꢣ
ꢩ
ꢛ
ꢤ
ꢡ
ꢣ
ꢢ
ꢛ
ꢢ
ꢞ
ꢟ
ꢜ
ꢥ
ꢪ
ꢡ
ꢜ
ꢢ
ꢢ
ꢦ
ꢣ
ꢋ
Copyright 2003, Texas Instruments Incorporated  
ꢟ
ꢞ
ꢤ
ꢢ
ꢞ
ꢟ
ꢠ
ꢢ
ꢞ
ꢣ
ꢧ
ꢛ
ꢝ
ꢛ
ꢤ
ꢦ
ꢟ
ꢢ
ꢫ
ꢢ
ꢦ
ꢟ
ꢞ
ꢝ
ꢬ
ꢡ
ꢗ
ꢜ
ꢠ
ꢦ
ꢣ
ꢢ
ꢡ
ꢜ
ꢪ
ꢡ
ꢟ
ꢪ
ꢭ
ꢡ
ꢢ ꢦ ꢣ ꢢꢛ ꢜꢯ ꢞꢝ ꢡ ꢩꢩ ꢧꢡ ꢟ ꢡ ꢠ ꢦ ꢢ ꢦ ꢟ ꢣ ꢋ  
ꢟ
ꢟ
ꢡ
ꢜ
ꢢ
ꢮ
ꢋ
ꢓ
ꢟ
ꢞ
ꢪ
ꢥ
ꢤ
ꢢ
ꢛ
ꢞ
ꢜ
ꢧ
ꢟ
ꢞ
ꢤ
ꢦ
ꢣ
ꢣ
ꢛ
ꢜ
ꢯ
ꢪ
ꢞ
ꢦ
ꢣ
ꢜ
ꢞ
ꢢ
ꢜ
ꢦ
ꢤ
ꢦ
ꢣ
ꢣ
ꢡ
ꢟ
ꢛ
ꢩ
ꢮ
ꢛ
ꢜ
ꢤ
ꢩ
ꢥ
ꢪ
ꢦ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...12

中文翻译

下载PDF

与SN74LVT125_06相关器件

型号 品牌 获取价格 描述 数据表
SN74LVT125D TI

获取价格

 		3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SN74LVT125DB TI

获取价格

 		3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SN74LVT125DBLE TI

获取价格

 		3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SN74LVT125DBR TI

获取价格

 		3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SN74LVT125DBRG4 TI

获取价格

 		3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SN74LVT125DG4 TI

获取价格

 		3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SN74LVT125DR TI

获取价格

 		3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SN74LVT125DRG4 TI

获取价格

 		3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SN74LVT125DW TI

获取价格

 		LVT SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDSO14, PLASTIC, SOP-14
SN74LVT125DWR TI

获取价格

 		LVT SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDSO14, PLASTIC, SOP-14

与SN74LVT125_06相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证